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Sun, 05 Jul 2026 05:08:23 -0700 (PDT) X-Received: by 2002:a17:90a:da83:b0:380:9052:f4b9 with SMTP id 98e67ed59e1d1-381122ebe5amr11701402a91.11.1783253303057; Sun, 05 Jul 2026 05:08:23 -0700 (PDT) Received: from [192.168.1.8] ([106.222.234.78]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31151fff32fsm6354185eec.21.2026.07.05.05.08.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 05 Jul 2026 05:08:22 -0700 (PDT) Message-ID: <81c657b0-7e61-4db3-b72c-46c213c707e9@oss.qualcomm.com> Date: Sun, 5 Jul 2026 17:38:13 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/8] drm/msm/a6xx: Increase HFI GX perf level limit to 24 To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Sean Paul , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20260705-kaana-gpu-dt-v2-0-6ac53de56314@oss.qualcomm.com> <20260705-kaana-gpu-dt-v2-1-6ac53de56314@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260705-kaana-gpu-dt-v2-1-6ac53de56314@oss.qualcomm.com> Content-Type: text/plain; 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Introduce > HFI_MAX_GX_LEVELS and use it to size the perf-table and bandwidth-table > GX vote arrays, and to derive GMU_MAX_GX_FREQS, so these levels are not > truncated. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 +- > drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 7 ++++--- > 2 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index 3f96b10b5f61..62e3fb230cd3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -20,7 +20,7 @@ struct a6xx_gmu_bo { > u64 iova; > }; > > -#define GMU_MAX_GX_FREQS 32 > +#define GMU_MAX_GX_FREQS HFI_MAX_GX_LEVELS > #define GMU_MAX_CX_FREQS 6 > #define GMU_MAX_BCMS 3 > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h > index e10d32ce93e0..f4da73a555c6 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h > @@ -5,6 +5,7 @@ > #define _A6XX_HFI_H_ > > #define HFI_MAX_QUEUES 3 > +#define HFI_MAX_GX_LEVELS 24 > > struct a6xx_hfi_queue_table_header { > u32 version; > @@ -119,7 +120,7 @@ struct a6xx_hfi_msg_perf_table_v1 { > u32 num_gpu_levels; > u32 num_gmu_levels; > > - struct perf_level gx_votes[16]; > + struct perf_level gx_votes[HFI_MAX_GX_LEVELS]; This will break older firmwares (A7x/6x). Luckily, A8x uses HFI_TABLE_GPU_PERF interface instead of this, which is more flexible. Will drop this patch. -Akhil. > struct perf_level cx_votes[4]; > } __packed; > > @@ -128,7 +129,7 @@ struct a6xx_hfi_msg_perf_table { > u32 num_gpu_levels; > u32 num_gmu_levels; > > - struct perf_gx_level gx_votes[16]; > + struct perf_gx_level gx_votes[HFI_MAX_GX_LEVELS]; > struct perf_level cx_votes[4]; > } __packed; > > @@ -144,7 +145,7 @@ struct a6xx_hfi_msg_bw_table { > u32 cnoc_cmds_addrs[6]; > u32 cnoc_cmds_data[2][6]; > u32 ddr_cmds_addrs[8]; > - u32 ddr_cmds_data[16][8]; > + u32 ddr_cmds_data[HFI_MAX_GX_LEVELS][8]; > } __packed; > > #define HFI_H2F_MSG_TEST 5 >