Re: [PATCH v2 2/4] drm/msm/a6xx: Add a bandwidth table for the Adreno 620 GMU

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/23/26 10:49 AM, Ishu Brar via B4 Relay wrote:
> From: Ishu Brar <patches@brar.si>
> 
> Without an A620 specific table the GMU falls back to the generic A630
> one, whose BCM addresses do not exist on SM7250, and the first GX
> performance vote times out.
> 
> Like the A650 one, send a single "off" entry just to get things running,
> with the BCM addresses looked up in cmd-db. This is only used while the
> GPU OPP table has no bandwidth levels; with them, the table is generated
> from the BCMs listed in the catalog entry. Add adreno_is_a620() for the
> selection.

Please just add the BCMs for your GPU:

.bcms = (const struct a6xx_bcm[]) {
	{ .name = "SH0", .buswidth = 16 },
	{ .name = "MC0", .buswidth = 4 },
	{
		.name = "ACV",
		.fixed = true,
		.perfmode = BIT(3),
	},
	{ /* sentinel */ }
};

You can factor it out since it's common across many a6xx GPUs
and &refer to it from the entry for a620

Konrad