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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f6747541bsm274402b3a.59.2026.04.14.18.21.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Apr 2026 18:21:25 -0700 (PDT) Message-ID: <81fdef8a-a60e-4d29-948d-c4a07e23dad9@oss.qualcomm.com> Date: Wed, 15 Apr 2026 09:21:21 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/9] coresight: etm4x: fix leaked trace id To: Yeoreum Yun , Leo Yan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com References: <20260413142003.3549310-1-yeoreum.yun@arm.com> <20260413142003.3549310-4-yeoreum.yun@arm.com> <20260414163221.GG356832@e132581.arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ZMynTViK3w0WVqCmEHTd3Xn3YSMhXw65 X-Proofpoint-GUID: ZMynTViK3w0WVqCmEHTd3Xn3YSMhXw65 X-Authority-Analysis: v=2.4 cv=K9gS2SWI c=1 sm=1 tr=0 ts=69dee817 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=7CQSdrXTAAAA:8 a=i5J-H8vbHws4jmN2WCEA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE1MDAxMCBTYWx0ZWRfX3PeoRm41+yX4 dROj5m099n4XoS2QgP6A28DE6EFD+0o/eDKlGRZ+dyaEl+3qJ6mLzjmHQv/6V7bvi4SIpL9VsvN Su8t4j8Jpd0NO8eGrDQaUgoEiIBOFiyTu0qz1wU4yv/s/KwZ0lts4xCpsKy4bWpbPc+Rmw8yDA2 CFunDgmDjjAu5Ruk2LDTH3W1PjJjBJc9KF9hUP0w2idcm599isoZh2JJidWpgTdszwZHvtFmP0B I2dMuLb99CeXe2oVEyWIv3oEO1JwHEfY3rA/MTL+pGgGbkmU8MNj8cEB36pbESwXxIvNJ57HF+T 3jRrnczN4q1WQI2OxE/wsdXQ6Aqdu4niQapU7xq9/gvjtjnaDv07s4lFLI6TyKNbQ+LvtEzMyYn fWqGB394W7DOt6PO8VMkPMvg/CBN9oc6aO35JbAgNzlYBhLuHqevh+TryJgxr1Apx11LNQ2rg18 UEMLaEi+eHdG/P0/F1g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-14_04,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604150010 On 4/15/2026 12:50 AM, Yeoreum Yun wrote: > Hi, > >> On Mon, Apr 13, 2026 at 03:19:56PM +0100, Yeoreum Yun wrote: >>> If etm4_enable_sysfs() fails in cscfg_csdev_enable_active_config(), >>> the trace ID may be leaked because it is not released. >>> >>> To address this, call etm4_release_trace_id() when etm4_enable_sysfs() >>> fails in cscfg_csdev_enable_active_config(). >>> >>> Signed-off-by: Yeoreum Yun >>> --- >>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> index 8ebfd3924143..1bc9f13e33f7 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> @@ -918,8 +918,10 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa >>> cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); >>> if (cfg_hash) { >>> ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); >>> - if (ret) >>> + if (ret) { >>> + etm4_release_trace_id(drvdata); >> >> I am not familiar with the trace ID, seems to me, it just allocate a ID >> for each tracer from the ID map and then always use this cached ID for >> the tracers. >> >> If so, even an ID is reserved for failures, and the ID map is big enough >> for each CPU, we don't need to worry memory leak or ID used out issue ? >> > > Agree. Practically, this is not a big issue and I don't think > because of this new id couldn't be allocated in 128 > although the one id is occupied by cpu while source is disabled. > > However, in theory, this could lead to an ID leak, > so it would be better to release it in error cases. Actually, the 128 Trace ID is not enough for allocating. That's why the TPDM devices share the trace ID of the connected TPDA devices. For the QCOM platform, we may got plenty of ETM devices (SoC with more than 20 Cores), lots of TPDM devices for each subsystem(CDSP, ADSP, GPU, GCC, MODEM, etc ...), and lots of dummy sources... What I am thinking is as SoCs continue to grow more complex with an increasing number of subsystems, trace IDs may be exhausted in the near future. (that's why we have dynamic trace ID allocation/release). Thanks, Jie > > [...] > > -- > Sincerely, > Yeoreum Yun