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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434ac9bfe1sm16026068b3a.12.2026.06.17.03.12.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jun 2026 03:13:01 -0700 (PDT) Message-ID: <82253653-bd85-45b8-8520-e2bb213ca48f@oss.qualcomm.com> Date: Wed, 17 Jun 2026 18:12:56 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] input: misc: Add Qualcomm SPMI PMIC haptics driver To: Konrad Dybcio , linux-arm-msm@vger.kernel.org, Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Stephen Boyd , Bjorn Andersson , Konrad Dybcio Cc: David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , kernel@oss.qualcomm.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260616-qcom-spmi-haptics-v1-0-d24e422de6b4@oss.qualcomm.com> <20260616-qcom-spmi-haptics-v1-3-d24e422de6b4@oss.qualcomm.com> <1bcf00ae-2558-4c3a-970d-aee1da0c06f9@oss.qualcomm.com> <29806448-0588-4590-8540-a689ccf1e7b0@oss.qualcomm.com> Content-Language: en-US From: Fenglin Wu In-Reply-To: <29806448-0588-4590-8540-a689ccf1e7b0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=F8hnsKhN c=1 sm=1 tr=0 ts=6a327331 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=3bJTXa-xiIkwHRLKEFYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDA5NSBTYWx0ZWRfX3/a56I+ilZ0G upW0bDgPelHb178BsSjzEXvDzbHKGeBoVbcSXH411motYgqLNokCHttXlIFnGfxkxONtiP8yusN LpsjDkdjhN52hJydnR/fi3ZV/F9gEWM= X-Proofpoint-GUID: wxUmu1ry5Sx46bViTg9_XEEZI8A6M1Vb X-Proofpoint-ORIG-GUID: wxUmu1ry5Sx46bViTg9_XEEZI8A6M1Vb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDA5NSBTYWx0ZWRfX3cJbBvfkHDad UUS98vwTBxjF31HKf7VluIMY5jrNPbdjhdx3Y7M3RQkm7xv2IUjEhLwpKdBanXps1HLCG6GoWJe i0bBBAfd6Vh094yIH8Kg46n5EgbU0yjcoIhd3sX5rhgSdT7zqNK8iQ0ibWhAUDm7JukGPtQDNd5 oeLzdQPB9yyx912kdkMSPysBQZke/Xo8OtHdfpWHAwDTHGUZAv/JGEHJPrzwk8Tpa7zcK5auMD1 /iRAb6M+oGOsAMXjO/Qo05W94agCtZhl664sohXZzClbMN62zELJk63m4A9b7Uvu2epUqfcQRgO Wx8JFPUvBo+z2m5qcYFbMX1mRwEmU9YC3Sa7FqjvwIyOKmHJ7eGmT2nMRYi+rCj7pjhJclEeQXC OQ69yDbWQKgqrapPANu+zco2s5U4MmAK1FZRHkrpu467OKKkmd/cbDTut7BI1j4TKjQoUxIDSxF Br5Zy57HE5RRdHlTwpw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170095 On 6/17/2026 5:30 PM, Konrad Dybcio wrote: > On 6/17/26 4:31 AM, Fenglin Wu wrote: >>>> +        ret = ptn_bulk_write(h, HAP_PTN_FIFO_DIN_0_REG, &data[i], 4); >>>> +        if (ret) >>>> +            return ret; >>>> +    } >>>> + >>>> +    for (; i < len; i++) { >>>> +        ret = ptn_write(h, HAP_PTN_FIFO_DIN_1B_REG, (u8)data[i]); >>>> +        if (ret) >>>> +            return ret; >>>> +    } >>> So if i'm reading this right, the first loop will always write >>> 4*(len//4) bytes and the second one will be entered at most once, >>> to write len rem 4 bytes.. should this be an if instead? >> I should put a comment for clarification. Here’s some background: FIFO data writing supports both 4-byte bulk writes using registers [HAP_PTN_FIFO_DIN_0_REG ... HAP_PTN_FIFO_DIN_3_REG], and 1-byte writes using the HAP_PTN_FIFO_DIN_1B_REG register. The 4-byte bulk write is more efficient, especially for waveform which has several Kb data, and it helps to reduce software latency when loading effects and reduce the delay in triggering vibration. It also helps prevent the FIFO from running dry during data refill in FIFO-empty interrupts. Typically, we use 4-byte writes for the initial 4-byte aligned data, and 1-byte writes for any trailing remainder. >> >> So it still needs a 'for' loop here since the remainder could be more than 1 byte. > Right, I mentioned len rem 4 but failed to notice it's a > single-byte write.. anyway, a comment here would be good > >>>> + >>>> +    return 0; >>>> +} >>>> + >>>> +/* >>>> + * Configure the hardware FIFO memory boundary. >>>> + * FIFO occupies addresses [0, fifo_len). >>>> + */ >>>> +static int haptics_configure_fifo_mmap(struct qcom_haptics *h) >>>> +{ >>>> +    u32 fifo_len, fifo_units; >>>> + >>>> +    /* Config all memory space for FIFO usage for now */ >>> What's the not-"for now" endgame for this? >> The hardware supports more modes than the two currently supported in the driver. One of these, called 'PAT_MEM' mode, also shares memory space with FIFO mode. However, 'PAT_MEM' requires memory to be pre-reserved and waveform data to be pre-loaded. The entire 8K bytes of memory can be divided into partitions, and it is configurable, with FIFO mode always using the first partition [0, fifo_len], where 'fifo_len' is set via the 'MMAP_FIFO_REG' register. 'PAT_MEM' mode plays waveform using data preloaded in a memory bank defined by the registers 'PATX_MEM_START_ADDR_REG' and 'PATTERN_SPMI_PATX_LEN_REG' (they are not defined in the driver). Since PAT_MEM is mainly intended for hardware-triggered vibrations, such as a signal from a dedicated GPIO triggering a short vibration with a preloaded waveform, and although it also supports software triggers, I haven't found a suitable way to support it well into the driver under input FF framework yet. So, I am currently allocating the >> entire 8K FIFO memory for FIFO mode only. We can adjust this later if we find a better way to incorporate 'PAT_MEM' mode into the driver. > Sounds like a plan. > > For the other mode, would that GPIO trigger need any OS intervention? > Could you speak a bit more about how that works? > > Konrad I'll try to clarify the 'PAT_MEM' mode further. 'PAT_MEM' is useful for latency-sensitive vibrations because it preloads the waveform into a fixed memory bank, then it doesn't need to load the data of the effect in the HW before triggering the play. When playback is triggered, it plays the waveform from the specified memory address and length. This memory should be preserved, and the data is preloaded during boot. Unlike FIFO mode, it doesn't allow data refilling. The trigger can come from hardware via dedicated GPIOs—currently, three are supported, each mapping to a memory bank set through specific registers. Software configuration can be done in the bootloader or in the driver probe, but the 'fifo_len' should be adjusted accordingly. After setup, software doesn't need to manage it further, relying on the GPIO signal to activate the playback (for example, a pressure sensor triggering vibration to simulate a physical key press). The trigger can also come from software using SPMI commands by setting the play mode, start address, and data length. I previously tried using the 'FF_HAPTIC' effect by mapping 'hid_usage' to a predefined effect in the devicetree, but later I found it unsuitable since 'FF_HAPTIC' is mainly for USB HID touch devices and not general vibration usage. If you have any suggestions for supporting 'PAT_MEM' mode through the input FF framework, please let me know.