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From: Hans de Goede <hdegoede@redhat.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
	Maxime Ripard <maxime.ripard@free-electrons.com>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80
Date: Mon, 30 May 2016 20:05:29 +0200	[thread overview]
Message-ID: <822dc3f1-9afe-f356-e0e7-89073586d401@redhat.com> (raw)
In-Reply-To: <CAGb2v65=ZM+deSmTmMnT6XFJv8PuY+Kba3kJGKrk_46hxxRyHA@mail.gmail.com>

Hi,

On 30-05-16 14:59, Chen-Yu Tsai wrote:
> On Mon, May 30, 2016 at 7:34 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 29-05-16 09:04, Chen-Yu Tsai wrote:
>>>
>>> The MMC clock timings were incorrectly calculated, when the conversion
>>> from delay value to delay phase was done.
>>>
>>> The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
>>> unusable. Unfortunately it seems different controllers on the same SoC
>>> have different timings. The new settings are taken from mmc2, which is
>>> commonly used with eMMC.
>>
>>
>> Hmm, I'm not really all that familiar with mmc, but can't an external
>> sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then
>> we really need to update the driver to use the right per controller
>> timings.
>
> I would very much like that to happen. However, SD card UHS-1 DDR modes
> require 1.8V signaling, which is unavailable on _all_ sunxi boards.
> This seems like a limit of most of the SoCs not having a separate IO
> voltage rail for mmc pins.
>
> Until then, I wouldn't worry that much.
>
>>> The settings for the slower timing modes seem to work despite being
>>> wrong, so leave them be.
>>
>>
>> If you're sure the timings are wrong, please fix them. Sometimes wrong
>> timings do seem to work, but lead to unreliable communication, or turn
>> out to work on some boards and not on others due to routing differences.
>
> Unfortunately I did try putting in the correct numbers for them, and my
> eMMC then failed to probe. It seems the core switches up from 400kHz to
> 50MHz then to 50MHz DDR, and it fails somewhere in there, maybe at 50MHz.
>
> I'm not sure if we need to add DT bindings to specify different delays
> for different controllers, though. Seems like we'll never actually use
> it.
>
> Hope this answers your questions.

Yes that answers my questions, and with my questions answered, this series is:

Acked-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans

  parent reply	other threads:[~2016-05-30 18:05 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-29  7:04 [PATCH 0/3] mmc: sunxi: Fix MMC DDR modes for Allwinner A80 Chen-Yu Tsai
2016-05-29  7:04 ` [PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher Chen-Yu Tsai
2016-05-31  9:30   ` Krzysztof Kozlowski
2016-06-01  1:25   ` Jaehoon Chung
2016-06-01  2:36   ` Shawn Lin
2016-06-01  9:19   ` Marcel Ziswiler
2016-06-01 18:58   ` Bjorn Andersson
2016-06-02  8:08     ` Chen-Yu Tsai
2016-06-02  8:31   ` Ulf Hansson
2016-06-02  9:35     ` Krzysztof Kozlowski
2016-06-02 15:01       ` Ulf Hansson
2016-05-29  7:04 ` [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80 Chen-Yu Tsai
2016-05-30 11:34   ` Hans de Goede
2016-05-30 12:59     ` Chen-Yu Tsai
2016-05-30 15:38       ` Chen-Yu Tsai
2016-05-30 18:05       ` Hans de Goede [this message]
2016-05-29  7:04 ` [PATCH 3/3] mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80 Chen-Yu Tsai

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