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b=lwRzPkl0OglN9C1lWxu8X1EKZJ1PcLF1zs+3zBH49XY3bhzhcyKM0zEJir0Ehaxq/YNarv9S7seOenzTZWjI150/LunzTGH5BCDYjgw/E+7bR7zQa6ykEniPg40JbCFgFQeKQEmi8jwDs47ki5MovemJF9jJKhToiFHZavZmutk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL1PR12MB5320.namprd12.prod.outlook.com (2603:10b6:208:314::17) by CH3PR12MB8403.namprd12.prod.outlook.com (2603:10b6:610:133::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.12; Tue, 15 Sep 2026 00:20:20 +0000 Received: from BL1PR12MB5320.namprd12.prod.outlook.com ([fe80::1876:4a6d:2cf5:b8d1]) by BL1PR12MB5320.namprd12.prod.outlook.com ([fe80::1876:4a6d:2cf5:b8d1%5]) with mapi id 15.21.0406.007; Tue, 15 Sep 2026 00:20:19 +0000 Message-ID: <82446f14-f961-4f8c-862f-b151f7e8f691@amd.com> Date: Mon, 14 Sep 2026 19:20:17 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] x86/resctrl: Fix ABMC counter programming for extended counter ranges To: Reinette Chatre , Babu Moger , tony.luck@intel.com, bp@alien8.de Cc: x86@kernel.org, Dave.Martin@arm.com, james.morse@arm.com, corbet@lwn.net, skhan@linuxfoundation.org, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, eranian@google.com, peternewman@google.com References: <9e85f67add9ac84f55e4b0fced92ed8994f8419a.1788545152.git.babu.moger@amd.com> <10240e0e-6879-4378-8763-cb1a9baf1f2d@amd.com> <30dc55d0-511d-4f5f-92df-5dd0add354a2@intel.com> Content-Language: en-US From: "Moger, Babu" In-Reply-To: <30dc55d0-511d-4f5f-92df-5dd0add354a2@intel.com> Content-Type: text/plain; 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Update the cntr_id field handling to support the full hardware ABMC >>>> counter range and ensure that counter programming does not interfere with >>>> unrelated counters. >>> >>> Sashiko's assessment that this statement is not accurate looks correct to me. >>> >>> Looks like the enumeration needs a check to limit the number of supported >>> counters if the hardware supports more than what can be configured? It seems >>> awkward that such hardware could exist and unclear why the spec has a mismatch in >> >> >> You're right. The spec overlooked this scenario. I've notified the concerned team. >> >> >> Do you want me add this check? >> >> -               r->mon.num_mbm_cntrs = (ebx & GENMASK(15, 0)) + 1; >> +               r->mon.num_mbm_cntrs = (ebx & GENMASK(12, 0)) + 1; >> > > Yes please. > >> >>> the number of bits here. Even if cntr_id expands further to use the remaining >>> reserved bits it would still not be sufficient to configure all the numbers >>> that hardware may claim to support. Are there perhaps more field width changes >>> in this upcoming spec update? >> >> Two fields(ctrl_id and bw_src) in here are changing for this register. I dont know about other changes yet. >> >>> >>>> >>>> 2. Expand the bw_src field to 15 bits. >>> >>> Do the comments describing the RMID field width when reading the monitoring >>> data (__cntr_id_read() and __rmid_read_phys()) need an update also? >> >> The RMID field width is expected to change. We can revisit this when that happens. > > > This patch is that change, no? bw_src is expanded to 15 bits, and bw_src contains > the RMID. > > This is the new RMID field width for monitoring configuration, after configuration > the counter needs to be read for the monitoring data via MSR_IA32_QM_EVTSEL and per > __cntr_id_read() the RMID field is still restricted (although not enforce by resctrl) > to 12 bits: > > * 43:32 RMID RMID or counter ID in ABMC mode > > resctrl also supports switching between "default" and "mbm_event" mode and there > is no support for the number of RMIDs changing between the modes ... this reading > an event in "default" mode should support the same number of RMIDs as > "mbm_event" mode and we see in __rmid_read_phys() (although, again not enforced) > that it supports even fewer bits for RMID > > IA32_QM_EVTSEL.RMID (bits 41:32) are configured with valid RMID > > Looks like after this patch there are quite a few different field widths for RMID > between what is documented, used directly, and actually enforced. > >>>> 3. Change "unsigned long" to u64 to fix truncation on 32-bit x86. >>> >>> Sashiko found that this change by itself is not sufficient to address issues >>> with 32-bit. What do you think of dropping this part of the patch and instead >>> adding your support to: >>> >>> https://lore.kernel.org/lkml/20260831174421.13921-22-tony.luck@intel.com/ ? >> >> Yes. I agree and support that approach. Looks like all the maintainers are inline with dropping 32. Will drop this change. > > If you do support that change, please consider adding a tag. Yes. Will do. Will review his code and test it. Thanks Babu