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b=XaBU3Ga27YwuE3MgOQHtzSgnGI2MJe1ggp/U6QxZ2ZxZhn2L6DgEn89+Q8ghL1soji9CVF ZOLYYKTUiNmbk9Cg== Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 5766413808; Fri, 19 Jul 2024 16:22:23 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id +aFTEr+Smma7FQAAD6G6ig (envelope-from ); Fri, 19 Jul 2024 16:22:23 +0000 Message-ID: <82472066-56a5-4f4f-8034-cf3a7afc206e@suse.de> Date: Fri, 19 Jul 2024 19:22:22 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] dt-bindings: interrupt-controller: Add bcm2712 MSI-X DT bindings To: Rob Herring , Stanimir Varbanov Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list , Thomas Gleixner , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell References: <20240626104544.14233-1-svarbanov@suse.de> <20240626104544.14233-2-svarbanov@suse.de> <20240628220521.GA274493-robh@kernel.org> Content-Language: en-US From: Stanimir Varbanov In-Reply-To: <20240628220521.GA274493-robh@kernel.org> Content-Type: text/plain; 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RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; DKIM_TRACE(0.00)[suse.de:+]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.de:dkim,suse.de:email] X-Spam-Level: X-Rspamd-Queue-Id: 560ED21198 X-Spam-Score: 0.20 X-Spam-Flag: NO X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Bar: / Hi Rob, Thank you for the comments! On 6/29/24 01:05, Rob Herring wrote: > On Wed, Jun 26, 2024 at 01:45:38PM +0300, Stanimir Varbanov wrote: >> Adds DT bindings for bcm2712 MSI-X interrupt peripheral controller. >> >> Signed-off-by: Stanimir Varbanov >> --- >> .../brcm,bcm2712-msix.yaml | 74 +++++++++++++++++++ >> 1 file changed, 74 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml >> new file mode 100644 >> index 000000000000..ca610e4467d9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml >> @@ -0,0 +1,74 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Broadcom bcm2712 MSI-X Interrupt Peripheral support >> + >> +maintainers: >> + - Stanimir Varbanov >> + >> +description: > >> + This interrupt controller is used to provide intterupt vectors to the > > typo Will fix it. > >> + generic interrupt controller (GIC) on bcm2712. It will be used as >> + external MSI-X controller for PCIe root complex. >> + >> +allOf: >> + - $ref: /schemas/interrupt-controller/msi-controller.yaml# >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - "brcm,bcm2712-mip-intc" > > Don't need quotes. Nor 'items'. And enum can be 'const' OK. > >> + reg: >> + maxItems: 1 >> + description: > >> + Specifies the base physical address and size of the registers > > drop. That's *every* reg property. OK. > >> + >> + interrupt-controller: true >> + >> + "#interrupt-cells": >> + const: 2 >> + >> + msi-controller: true > > Add #msi-cells. The default is 0, but that's legacy. OK. > >> + >> + brcm,msi-base-spi: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: The SGI number that MSIs start. >> + >> + brcm,msi-num-spis: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: The number of SGIs for MSIs. >> + >> + brcm,msi-offset: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: Shift the allocated MSIs up by N. > > If only we had a property that every MSI controller seems to need. Go > check msi-controller.yaml... This exists because the second instance of MIP MSI-X interrupt-controller (mip1) has some limitations. Snippet from donwstream dtsi: brcm,msi-base-spi = <247>; /* Actually 20 total, but the others are * both sparse and non-consecutive */ brcm,msi-num-spis = <8>; brcm,msi-offset = <8>; brcm,msi-pci-addr = <0xff 0xffffe000>; I don't know how to model this except private property. > >> + >> + brcm,msi-pci-addr: >> + $ref: /schemas/types.yaml#/definitions/uint64 >> + description: MSI-X message address. > > Why don't other platforms need something like this? This is a destination address for MSI mem writes from PCIe endpoint devices, i.e. msi_msg.address filled when composing msi_msg (irq_chip::irq_compose_msi_msg). ~Stan > >> + >> +additionalProperties: false >> + >> +required: >> + - compatible >> + - reg >> + - interrupt-controller >> + - "#interrupt-cells" >> + - msi-controller >> + >> +examples: >> + - | >> + msi-controller@130000 { >> + compatible = "brcm,bcm2712-mip-intc"; >> + reg = <0x00130000 0xc0>; >> + msi-controller; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + brcm,msi-base-spi = <128>; >> + brcm,msi-num-spis = <64>; >> + brcm,msi-offset = <0>; >> + brcm,msi-pci-addr = <0xff 0xfffff000>; >> + }; >> -- >> 2.43.0 >>