Re: [PATCH 09/21] amd64_edac: assign DRAM chip select base and mask in a family-specific way

[Doug Thompson <norsk5@yahoo.com>]

--- On Mon, 5/4/09, Mauro Carvalho Chehab <mchehab@redhat.com> wrote:

> From: Mauro Carvalho Chehab <mchehab@redhat.com>
> Subject: Re: [PATCH 09/21] amd64_edac: assign DRAM chip select base and mask in a family-specific way
> To: "Borislav Petkov" <borislav.petkov@amd.com>
> Cc: akpm@linux-foundation.org, greg@kroah.com, mingo@elte.hu, tglx@linutronix.de, hpa@zytor.com, dougthompson@xmission.com, linux-kernel@vger.kernel.org
> Date: Monday, May 4, 2009, 3:59 PM
> Borislav Petkov escreveu:
> > +    for (cs = 0; cs <
> CHIPSELECT_COUNT; cs++) {
> > +        reg = K8_DCSB0
> + (cs * 4);
> > +        err =
> pci_read_config_dword(pvt->dram_f2_ctl, reg,
> > +       
>            
>     &pvt->dcsb0[cs]);
> > +        if (err != 0)
> > +       
>     debugf0("%s() Reading K8_DCSB0[%d]
> failed\n",
> > +       
>         __func__, cs);
> > +
> > +        debugf0(" 
> DCSB0[%d]=0x%08x reg: F2x%x\n",
> > +       
>     cs, pvt->dcsb0[cs], reg);
> >   
> 
> Hmm... I suspect that there's a missing else before the
> debugf0(). If you got an error while reading it, you
> shouldn't be showing the results. 
> > +
> > +        /* If DCT are
> NOT ganged, then read in DCT1's base */
> > +        if
> (boot_cpu_data.x86 >= 0x10 &&
> !dct_ganging_enabled(pvt)) {
> > +       
>     reg = F10_DCSB1 + (cs * 4);
> > +       
>     err =
> pci_read_config_dword(pvt->dram_f2_ctl, reg,
> > +       
>            
>        
> &pvt->dcsb1[cs]);
> > +       
>     if (err != 0)
> > +       
>         debugf0("%s() Reading
> F10_DCSB1[%d] failed\n",
> > +       
>            
> __func__, cs);
> > +       
>     debugf0("  DCSB1[%d]=0x%08x reg:
> F2x%x\n",
> > +       
>         cs, pvt->dcsb1[cs],
> reg);
> >   
> The same issue here: if you got an error while reading it,
> you shouldn't be showing the results. 
> Cheers,
> Mauro.
> 

An 'else' could be inserted, but it is only under DEBUG state for development purposes.  

BACKGROUND: The error checking of the pci config space read was added during the time when the kernel couldn't read the extended 4k config space via the AMD IOConfig port access function (12 bits of offset) not via MMCONFIG. 

doug t