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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b98335ddfa1sm471236266b.32.2026.03.23.04.07.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Mar 2026 04:07:08 -0700 (PDT) Message-ID: <82b1c902-3695-4b19-8995-69a2b31b913b@oss.qualcomm.com> Date: Mon, 23 Mar 2026 12:07:06 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/3] arm64: dts: qcom: Introduce sa8255p SoC To: Deepti Jaggi , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Sodagudi , Nikunj Kela , Shazad Hussain References: <20260304-b4-scmi-upstream-v5-0-f8fc763d8da0@oss.qualcomm.com> <20260304-b4-scmi-upstream-v5-2-f8fc763d8da0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=RMC+3oi+ c=1 sm=1 tr=0 ts=69c11ede cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=-3HSSwHb9ON-QZMGylwA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: p4Ow_zNPjLbWIDCNd3iNRlQH3XIOvMO6 X-Proofpoint-GUID: p4Ow_zNPjLbWIDCNd3iNRlQH3XIOvMO6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDA4NiBTYWx0ZWRfX7u3zqB2ishB1 Xxha3s84iA9eGs5CyPWVPJ/3WGAjY0LT+KmxomjagfxSvNHw0S6xt8SsWSUcYEw0DyKsWwGvmzl 44ecBy4HZOfX49a4U0wqfRZTceJYj99AbqMFOY699+7vL9UuWvXra9cvVMzVmo2Me+bOVM2sfCw 6y2sh4ZTVYn+M2tB7ZfOkkUDbzgspN+D0DVKlMiBmUL2K5Hlj4sgEePKEXK/CXTzxGhbbSCkKbM X04QoKAF/hwDVYQ9FeOM+FUhPaHVJukXyvxGHuJ/eqGodZI33ZgGsa/0elos1B+stBy0GAmq4TO qkE06fsFeTItudISgaJd7wDZ8jtIF0WWVFRssL/NRfy4cKs2AOv+7SxXsX5IewwAB6ZJzSGrXJk rt5dZAB/F0qUQKZ1kk9yPk8BcsyEWBlygXNqXkaZeLV9EQtg9iMkeugVpkNhoVyZLPU66g2OBMp 1pASh4kTEiGi9eyHHVQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_03,2026-03-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230086 On 3/17/26 12:58 AM, Deepti Jaggi wrote: > > On 3/11/2026 6:41 AM, Konrad Dybcio wrote: >> On 3/5/26 5:28 AM, Deepti Jaggi wrote: >>> From: Nikunj Kela >>> >>> Introduce base device tree support for sa8255p Qualcomm's automotive >>> infotainment SoC. The base dt file describes core SoC components- CPUs, >>> CPU map, ipcc, QUP, geni UART, interrupt controller, TLMM, reserved >>> memory, SMMU, firmware scm, scmi, watchdog, SRAM, PSCI, ufs, pcie, pmu >>> nodes and enable booting to shell with ramdisk. >>> >>> The Qualcomm automotive sa8255p SoC utilizes firmware to configure >>> platform resources such as clocks, interconnects, and TLMM. Device drivers >>> request these resources through the SCMI power,reset and performance >>> protocols. Assign each device driver a dedicated SCMI channel and Tx/Rx >>> doorbells to support parallel resource requests and aggregation in the >>> SCMI platform server. Operate the SCMI server stack in an SMP-enabled VM, >>> using the Qualcomm SMC/HVC transport driver for communication. >>> >>> Group resource operations to improve abstraction and reduce the number of >>> SCMI requests. Follow the SCMI-based resource management approach >>> demonstrated by Qualcomm at LinaroConnect 2024.[1] >>> >>> Limit initial support to basic platform resources, serial console, ufs >>> and pcie.Defer enabling USB, and Ethernet to subsequent updates. >>> >>> [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte >>> >>> Co-developed-by: Shazad Hussain >>> Signed-off-by: Shazad Hussain >>> Signed-off-by: Nikunj Kela >>> Co-developed-by: Deepti Jaggi >>> Signed-off-by: Deepti Jaggi >>> --- >> [...] > > Thanks for reviewing the series . > >>> + tsens2: thermal-sensor@c251000 { >>> + compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2"; >>> + reg = <0x0 0x0c251000 0x0 0x1ff>, >>> + <0x0 0x0c224000 0x0 0x8>; >> All TSENS regions are 0x1000-long >> >> [...] > > Ack > >> >>> + tlmm: pinctrl@f000000 { >>> + compatible = "qcom,sa8255p-tlmm", "qcom,sa8775p-tlmm"; >>> + reg = <0x0 0x0f000000 0x0 0x1000000>; >>> + interrupts = ; >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + gpio-ranges = <&tlmm 0 0 149>; >>> + wakeup-parent = <&pdc>; >>> + }; >> Praveen suggested GPIOs are not controlled by Linux: >> >> https://lore.kernel.org/linux-arm-msm/12063990-70fe-4faf-89fa-c74c7bd97f42@oss.qualcomm.com/ >> >> Could you comment on this? >> >> [...] > > For buses,FW is handling, but for PCIe and ethernet , pin configuration is controlled by Linux. Okay, does the firmware synchronize/access-control access based on the pin index, so that e.g. the gpioset utility won't be able to mess with the desired state? Or do we need something like gpio-reserved-ranges for the FW-managed ones? Konrad