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From: Jinlong Mao <quic_jinlmao@quicinc.com>
To: Mike Leach <mike.leach@linaro.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	<coresight@lists.linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Tingwei Zhang <quic_tingweiz@quicinc.com>,
	Yuanfang Zhang <quic_yuanfang@quicinc.com>,
	Tao Zhang <quic_taozha@quicinc.com>,
	Trilok Soni <quic_tsoni@quicinc.com>,
	Hao Zhang <quic_hazha@quicinc.com>,
	<linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support
Date: Wed, 20 Apr 2022 22:41:12 +0800	[thread overview]
Message-ID: <82bb1da8-7a44-8fdf-d9d5-b3c11a936887@quicinc.com> (raw)
In-Reply-To: <CAJ9a7ViDkaqykQTiPX7T7z0T0cDOfnyDM6H7sY=dNDe0DqZwDw@mail.gmail.com>

Thank you Mike for the review.

On 4/19/2022 5:23 PM, Mike Leach wrote:
> Hi,
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> TPDM serves as data collection component for various dataset types.
>> DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
>> can be enabled for data collection by writing 1 to the first bit of
>> DSB_CR register. This change is to add enable/disable function for
>> DSB dataset by writing DSB_CR register.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-tpdm.c | 61 ++++++++++++++++++++
>>   drivers/hwtracing/coresight/coresight-tpdm.h | 21 +++++++
>>   2 files changed, 82 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
>> index 3900ae50670a..d7b970cdcf51 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>> @@ -20,7 +20,28 @@
>>
>>   DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
>>
>> +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
>> +{
>> +       u32 val;
>> +
>> +       /* Set the enable bit of DSB control register to 1 */
>> +       val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
>> +       val = val | BIT(0);
> Please use #defined values, declared in the header file rather than
> BIT(x) here. (the etm4x drivers have been recently updated to use the
> same pattern).
> e.g.
>   val |= TPDM_DSB_CR_ENA;
I will update in next version.
>> +       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
>> +}
>> +
>>   /* TPDM enable operations */
>> +static void _tpdm_enable(struct tpdm_drvdata *drvdata)
>> +{
>> +       CS_UNLOCK(drvdata->base);
>> +
>> +       /* Check if DSB datasets is present for TPDM. */
>> +       if (test_bit(TPDM_DS_DSB, drvdata->datasets))
>> +               tpdm_enable_dsb(drvdata);
>> +
>> +       CS_LOCK(drvdata->base);
>> +}
>> +
>>   static int tpdm_enable(struct coresight_device *csdev,
>>                         struct perf_event *event, u32 mode)
>>   {
>> @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
>>                  return -EBUSY;
>>          }
>>
>> +       _tpdm_enable(drvdata);
>>          drvdata->enable = true;
>>          mutex_unlock(&drvdata->lock);
>>
>> @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
>>          return 0;
>>   }
>>
>> +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
>> +{
>> +       u32 val;
>> +
>> +       /* Set the enable bit of DSB control register to 0 */
>> +       val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
>> +       val = val & ~BIT(0);
> val &= ~TPDM_DSB_CR_ENA;
I will update in next version.
>
>> +       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
>> +}
>> +
>>   /* TPDM disable operations */
>> +static void _tpdm_disable(struct tpdm_drvdata *drvdata)
>> +{
>> +       CS_UNLOCK(drvdata->base);
>> +
>> +       /* Check if DSB datasets is present for TPDM. */
>> +       if (test_bit(TPDM_DS_DSB, drvdata->datasets))
>> +               tpdm_disable_dsb(drvdata);
>> +
>> +       CS_LOCK(drvdata->base);
>> +
>> +}
>> +
>>   static void tpdm_disable(struct coresight_device *csdev,
>>                           struct perf_event *event)
>>   {
>> @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
>>                  return;
>>          }
>>
>> +       _tpdm_disable(drvdata);
>>          drvdata->enable = false;
>>          mutex_unlock(&drvdata->lock);
>>
>> @@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops = {
>>          .source_ops     = &tpdm_source_ops,
>>   };
>>
>> +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
>> +{
>> +       int i;
>> +       u32 pidr;
>> +
>> +       CS_UNLOCK(drvdata->base);
>> +       /*  Get the datasets present on the TPDM. */
>> +       pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
>> +       for (i = 0; i < TPDM_DATASETS; i++) {
>> +               if (pidr & BIT(i))
>> +                       __set_bit(i, drvdata->datasets);
> Could this be considerably simpified? - there are a maximum of 7 bits
> for datasets - and you are setting the same bit in drvdata->datasets
> for each bit in pidr
>
> e.g. if the datasets declaration is a simple unsigned long, then the
> following is easier to read and understand:
>
> drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);
>
> The tests above could then become:
> if (drvdata->datasets & BIT(TPDM_DS_DSB)) ...
>
I will check your suggestion and update in next version.
>> +       }
>> +       CS_LOCK(drvdata->base);
>> +}
>> +
>>   static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>>   {
>>          struct device *dev = &adev->dev;
>> @@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>>          if (IS_ERR(drvdata->csdev))
>>                  return PTR_ERR(drvdata->csdev);
>>
>> +       tpdm_init_default_data(drvdata);
>>          /* Decrease pm refcount when probe is done.*/
>>          pm_runtime_put(&adev->dev);
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
>> index 94a7748a5426..8f05070879c4 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
>> @@ -6,6 +6,25 @@
>>   #ifndef _CORESIGHT_CORESIGHT_TPDM_H
>>   #define _CORESIGHT_CORESIGHT_TPDM_H
>>
>> +/* The max number of the datasets that TPDM supports */
>> +#define TPDM_DATASETS       7
>> +
>> +/* DSB Subunit Registers */
>> +#define TPDM_DSB_CR            (0x780)
>> +
> declare the enable bit here with comment documenting usage  - see above.
>
>> +/**
>> + * This enum is for PERIPHIDR0 register of TPDM.
>> + * The fields [6:0] of PERIPHIDR0 are used to determine what
>> + * interfaces and subunits are present on a given TPDM.
>> + *
>> + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
>> + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
>> + */
>> +enum tpdm_dataset {
>> +       TPDM_DS_IMPLDEF,
>> +       TPDM_DS_DSB,
>> +};
>> +
>>   /**
>>    * struct tpdm_drvdata - specifics associated to an TPDM component
>>    * @base:       memory mapped base address for this component.
>> @@ -13,6 +32,7 @@
>>    * @csdev:      component vitals needed by the framework.
>>    * @lock:       lock for the enable value.
>>    * @enable:     enable status of the component.
>> + * @datasets:   The datasets types present of the TPDM.
>>    */
>>
>>   struct tpdm_drvdata {
>> @@ -21,6 +41,7 @@ struct tpdm_drvdata {
>>          struct coresight_device *csdev;
>>          struct mutex            lock;
>>          bool                    enable;
>> +       DECLARE_BITMAP(datasets, TPDM_DATASETS);
> Could this simply be declared as an unsigned long? - then simplify the
> code in the .c file.
>
> Regards
>
> Mike
>
>>   };
>>
>>   #endif  /* _CORESIGHT_CORESIGHT_TPDM_H */
>> --
>> 2.17.1
>>
>

  reply	other threads:[~2022-04-20 14:41 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
2022-04-12 12:50 ` [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths Mao Jinlong
2022-04-14 14:20   ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 02/10] Coresight: Add coresight TPDM source driver Mao Jinlong
2022-04-14 14:53   ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
2022-04-14 15:22   ` Mike Leach
2022-04-15  9:56     ` Jinlong Mao
2022-04-12 12:50 ` [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
2022-04-19  9:23   ` Mike Leach
2022-04-20 14:41     ` Jinlong Mao [this message]
2022-04-12 12:50 ` [PATCH v5 05/10] coresight-tpdm: Add integration test support Mao Jinlong
2022-04-13 13:57   ` Mike Leach
2022-04-13 16:53     ` Jinlong Mao
2022-04-12 12:50 ` [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong
2022-04-19  9:25   ` Mike Leach
2022-04-20 14:42     ` Jinlong Mao
2022-04-12 12:50 ` [PATCH v5 07/10] Coresight: Add TPDA link driver Mao Jinlong
2022-04-19  9:51   ` Mike Leach
2022-04-20 14:43     ` Jinlong Mao
2022-04-12 12:50 ` [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong
2022-04-19  8:32   ` Mike Leach
2022-04-20 14:37     ` Jinlong Mao
2022-04-12 12:50 ` [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
2022-04-13  9:58   ` Konrad Dybcio
2022-04-13 16:45     ` Jinlong Mao
2022-04-14 13:40       ` Mike Leach
2022-04-15  9:53         ` Jinlong Mao
2022-04-20 17:07           ` Konrad Dybcio
2022-04-12 12:50 ` [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250 Mao Jinlong
2022-04-13 10:01   ` Konrad Dybcio

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