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Fri, 13 Mar 2026 07:14:45 -0700 (PDT) Message-ID: <82d2d515a38eabd78951effff1dbc459db864130.camel@linaro.org> Subject: Re: [PATCH v7 04/10] dt-bindings: soc: google: gs101-pmu: allow power domains as children From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Rob Herring Cc: Krzysztof Kozlowski , Alim Akhtar , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown , Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Date: Fri, 13 Mar 2026 14:15:31 +0000 In-Reply-To: References: <20260306-gs101-pd-v7-0-03f7c7965ba5@linaro.org> <20260306-gs101-pd-v7-4-03f7c7965ba5@linaro.org> <20260312151228.GA3136988-robh@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8+build1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2026-03-13 at 08:26 -0500, Rob Herring wrote: > On Fri, Mar 13, 2026 at 5:48=E2=80=AFAM Andr=C3=A9 Draszik wrote: > >=20 > > On Thu, 2026-03-12 at 10:12 -0500, Rob Herring wrote: > > > On Fri, Mar 06, 2026 at 10:29:55AM +0000, Andr=C3=A9 Draszik wrote: > > >=20 > > > > =C2=A0=C2=A0=C2=A0=C2=A0 system-controller@17460000 { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible =3D "go= ogle,gs101-pmu"; > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg =3D <0x1746000= 0 0x10000>; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #address-cells =3D <1>; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #size-cells =3D <1>; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ranges; > > > >=20 > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 google,pmu-intr-ge= n-syscon =3D <&pmu_intr_gen>; > > > > + > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pd_g3d: power-domain@1e= 00 { > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= compatible =3D "google,gs101-pd"; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= reg =3D <0x1e00 0x80>; > > >=20 > > > I'm assuming 0x1e00 is an offset from 0x17460000. That's not what ran= ges > > > says though. It says both addresses are in the same address space > > > (system-controller@17460000 parent's address space). You need: > > >=20 > > > ranges =3D <0x0 0x17460000 0x10000>; > >=20 > > Thanks Rob! On gs101, the PD driver can not do direct mmio. Instead it > > needs to use the regmap that the parent has created and apply the > > offset from the PD's reg property (using struct resource::start) > > (patch 7). > >=20 > > When using ranges as per your suggestion that doesn't work anymore, > > as resource->start isn't the offset anymore but the final physical > > address, and using that in combination with the parent's regmap > > doesn't give us the right address anymore. >=20 > You are mixing kernel implementation details and h/w. Just trying to get to the best solution, considering both. > Are the > registers in the child nodes MMIO or not? If not, then drop ranges. If > they are, then what I suggested for ranges is correct. While they are MMIO in theory and offsets into the parent's address space, in practice access from the OS is not possible via mmio APIs, only via the custom regmap created by the parent (which defers to the EL3 firmware) - hence the driver's need for the offset from the parent's base address. > For MMIO, your kernel implementation options are what you suggested, > do a regmap for each child, or use of_property_read_reg(). OK, I'll go with the first option then, thanks for your patience Rob! Cheers, Andre'