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[83.9.29.233]) by smtp.gmail.com with ESMTPSA id t3-20020a19ad03000000b004fa52552c82sm1733406lfc.155.2023.06.28.04.08.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jun 2023 04:08:11 -0700 (PDT) Message-ID: <82ed84aa-6335-c0fd-9c3e-1a6ef6924336@linaro.org> Date: Wed, 28 Jun 2023 13:08:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH V2 4/5] clk: qcom: gcc-qdu1000: Add support for GDSCs Content-Language: en-US To: Imran Shaik , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Taniya Das , Melody Olvera , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona , Satya Priya Kakitapalli , Ajit Pandey References: <20230628092837.3090801-1-quic_imrashai@quicinc.com> <20230628092837.3090801-5-quic_imrashai@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230628092837.3090801-5-quic_imrashai@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28.06.2023 11:28, Imran Shaik wrote: > Add the GDSCs support for QDU1000 and QRU1000 SoCs. > > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > Signed-off-by: Imran Shaik > --- Reviewed-by: Konrad Dybcio Konrad > Changes since v1: > - Newly added > > drivers/clk/qcom/gcc-qdu1000.c | 42 ++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c > index 991fb2bc97e9..718c34dca6e8 100644 > --- a/drivers/clk/qcom/gcc-qdu1000.c > +++ b/drivers/clk/qcom/gcc-qdu1000.c > @@ -17,6 +17,7 @@ > #include "clk-regmap-divider.h" > #include "clk-regmap-mux.h" > #include "clk-regmap-phy-mux.h" > +#include "gdsc.h" > #include "reset.h" > > enum { > @@ -2409,6 +2410,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { > }, > }; > > +static struct gdsc pcie_0_gdsc = { > + .gdscr = 0x9d004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "gcc_pcie_0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > +static struct gdsc pcie_0_phy_gdsc = { > + .gdscr = 0x7c004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x2, > + .pd = { > + .name = "gcc_pcie_0_phy_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > +static struct gdsc usb30_prim_gdsc = { > + .gdscr = 0x49004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > + .pd = { > + .name = "gcc_usb30_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > static struct clk_regmap *gcc_qdu1000_clocks[] = { > [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr, > [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr, > @@ -2545,6 +2579,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = { > [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr, > }; > > +static struct gdsc *gcc_qdu1000_gdscs[] = { > + [PCIE_0_GDSC] = &pcie_0_gdsc, > + [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, > + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, > +}; > + > static const struct qcom_reset_map gcc_qdu1000_resets[] = { > [GCC_ECPRI_CC_BCR] = { 0x3e000 }, > [GCC_ECPRI_SS_BCR] = { 0x3a000 }, > @@ -2606,6 +2646,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = { > .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks), > .resets = gcc_qdu1000_resets, > .num_resets = ARRAY_SIZE(gcc_qdu1000_resets), > + .gdscs = gcc_qdu1000_gdscs, > + .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs), > }; > > static const struct of_device_id gcc_qdu1000_match_table[] = {