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Fri, 22 Nov 2024 07:16:45 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AM7GjAR026282 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 07:16:45 GMT Received: from [10.216.2.20] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 23:16:40 -0800 Message-ID: <82fc7b99-bc3e-4a9b-a472-c1b70671f21a@quicinc.com> Date: Fri, 22 Nov 2024 12:46:37 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V5 1/4] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P To: Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Mike Tipton , Sibi Sankar , , , , References: <20241121113006.28520-1-quic_rlaggysh@quicinc.com> <20241121113006.28520-2-quic_rlaggysh@quicinc.com> <10e4fd4e-559d-4164-ab94-d5f0a60ffc22@quicinc.com> <53876db8-4401-481d-8684-af7e135d481e@kernel.org> Content-Language: en-US From: Raviteja Laggyshetty In-Reply-To: <53876db8-4401-481d-8684-af7e135d481e@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tpQHuPRYC9LisQ4lqI77GbTVtwFSu45O X-Proofpoint-ORIG-GUID: tpQHuPRYC9LisQ4lqI77GbTVtwFSu45O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220059 On 11/21/2024 11:20 PM, Krzysztof Kozlowski wrote: > On 21/11/2024 18:43, Raviteja Laggyshetty wrote: >> >> >> On 11/21/2024 5:23 PM, Krzysztof Kozlowski wrote: >>> On 21/11/2024 12:30, Raviteja Laggyshetty wrote: >>>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on >>>> SA8775P SoCs. >>> >>> This we see from the diff. Explain the hardware, why adding epps-l3-perf. >>> >> The EPSS instance in SA8775P uses PERF_STATE register instead of REG_L3_VOTE to scale L3 clocks.Along with SoC specific compatible, add new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based L3 scaling. > > Pasting the same replies as you pasted to others won't solve the > problem. Solve the problem - fix the commit msg. > >> >>>> >>>> Signed-off-by: Raviteja Laggyshetty >>>> --- >>>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>> index 21dae0b92819..042ca44c32ec 100644 >>>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >>>> @@ -34,6 +34,10 @@ properties: >>>> - qcom,sm8250-epss-l3 >>>> - qcom,sm8350-epss-l3 >>>> - const: qcom,epss-l3 >>>> + - items: >>>> + - enum: >>>> + - qcom,sa8775p-epss-l3 >>>> + - const: qcom,epss-l3-perf >>> >>> I don't understand this change in context of driver. These are the same. >>> Isn't this compatible with sm8250? >>> >> >> The intention for adding "qcom,epss-l3-perf" generic compatible is to use it for the chipsets which use perf state register for l3 scaling. >> Using generic compatible avoids the need for adding chipset specific compatible in match table. > > > Not true, specific compatibles used as fallback do the same and is a > preferred way. > Will make use of sm8250 compatibles for sa8775p in the next patch revision. > >> But received comment from konrad to add both SoC-specific and generic compatibles. > > I went through the history and don't see anything like that. Point to > the specific email please, if you disagree. > https://patchwork.kernel.org/project/linux-pm/patch/20241026123058.28258-2-quic_rlaggysh@quicinc.com/#26104591 >> Dmitry has suggested to update generic comaptibles for sc7280 and sm8250 SoCs, which makes use of perf state registers. > > OK > >> It will be done as separate patch series. > > No. I expect to see full, correct picture, not half baked patches which > contradict what is in current code. > > Ok, I will update the generic compatibles for sm8250, sc7280 SoCs in the next patch revision and will include them along with sa8775p dt patch. > Best regards, > Krzysztof