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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c82bbesm9029265ad.35.2025.12.18.20.54.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Dec 2025 20:54:05 -0800 (PST) Message-ID: <83130e02-4510-41d8-be5c-bbe9ad49dba1@oss.qualcomm.com> Date: Fri, 19 Dec 2025 12:53:59 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tao Zhang References: <20251028-configure_tpda_reg-v4-0-23000805d21d@oss.qualcomm.com> <20251028-configure_tpda_reg-v4-1-23000805d21d@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=NODYOk6g c=1 sm=1 tr=0 ts=6944da6f cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=-IRLh56tHnBc2i77m7MA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: g1e1rpi50jLsx7EDpxbEbmhoXM0o0nH0 X-Proofpoint-GUID: g1e1rpi50jLsx7EDpxbEbmhoXM0o0nH0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDAzOCBTYWx0ZWRfX5IEAlK1HSCtN ENd1NeyFrTPP3qCDS+cJGfED9mNvjdPDG3XlONXpVvhtYubiu6QlYXqMqhcF4U6qMAV1obWv3rh ezhwv9mTWoRALYVBgyd6CaUAO2BeN3nd5QIpNhTxP2eirzNwWIMMsA0X24vRfInqeN+cKfBjPTH k+5Xt2ZHmhsxUXBD3InVHRnD4elsqCTWOv2PVojvL97FAXB6Ay9M6TRY1Ohqen22fn7/ClJ8JCT pOKhIU2R6/8zGM8jdid9VkgA0pga+dueBfV20me7sUKal4cToAiIgbYKhF3+rcvfzQmhxCy3KE/ KCxTtLQ5JrjRcQZcy7AY7mb/0rybA2Uxs0VSZVt3ahVfMYWmbhhRW6FqORMedClDU5wYyC83Tgl MGRJZEGMWyEth0sfk12FUs4oD/G2rwj6SF9bTTWNnWS8icSwjlZSbisZfwCEg0sm+HWokfL2rJ6 PNw8rud5uXQY0xMZDEA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190038 On 12/18/2025 7:20 PM, Suzuki K Poulose wrote: > On 18/12/2025 11:10, Suzuki K Poulose wrote: >> On 28/10/2025 02:02, Jie Gan wrote: >>> From: Tao Zhang >>> >>> Introduce sysfs nodes to configure cross-trigger parameters for TPDA. >>> These registers define the characteristics of cross-trigger packets, >>> including generation frequency and flag values. >>> >>> Signed-off-by: Tao Zhang >>> Reviewed-by: James Clark >>> Co-developed-by: Jie Gan >>> Signed-off-by: Jie Gan >>> --- >>>   .../ABI/testing/sysfs-bus-coresight-devices-tpda   |  43 ++++ >>>   drivers/hwtracing/coresight/coresight-tpda.c       | 230 ++++++++++ >>> + ++++++++++ >>>   drivers/hwtracing/coresight/coresight-tpda.h       |  27 ++- >>>   3 files changed, 299 insertions(+), 1 deletion(-) >>> >>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >>> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> new file mode 100644 >>> index 000000000000..80e4b05a1ab4 >>> --- /dev/null >>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >>> @@ -0,0 +1,43 @@ >>> +What:        /sys/bus/coresight/devices//trig_async_enable >>> +Date:        October 2025 >>> +KernelVersion:    6.19 >>> +Contact:    Jinlong Mao , Tao Zhang >>> , Jie Gan >>> +Description: >>> +        (RW) Enable/disable cross trigger synchronization sequence >>> interface. >>> + >>> +What:        /sys/bus/coresight/devices//trig_flag_ts_enable >>> +Date:        October 2025 >>> +KernelVersion:    6.19 >>> +Contact:    Jinlong Mao , Tao Zhang >>> , Jie Gan >>> +Description: >>> +        (RW) Enable/disable cross trigger FLAG packet request >>> interface. >>> + >>> +What:        /sys/bus/coresight/devices//trig_freq_enable >>> +Date:        October 2025 >>> +KernelVersion:    6.19 >>> +Contact:    Jinlong Mao , Tao Zhang >>> , Jie Gan >>> +Description: >>> +        (RW) Enable/disable cross trigger FREQ packet request >>> interface. >>> + >>> +What:        /sys/bus/coresight/devices//freq_ts_enable >>> +Date:        October 2025 >>> +KernelVersion:    6.19 >>> +Contact:    Jinlong Mao , Tao Zhang >>> , Jie Gan >>> +Description: >>> +        (RW) Enable/disable the timestamp for all FREQ packets. >>> + >>> +What:        /sys/bus/coresight/devices//global_flush_req >>> +Date:        October 2025 >>> +KernelVersion:    6.19 >>> +Contact:    Jinlong Mao , Tao Zhang >>> , Jie Gan >>> +Description: >>> +        (RW) Set global (all ports) flush request bit. The bit >>> remains set until a >>> +        global flush request sequence completes. >>> + >>> +What:        /sys/bus/coresight/devices//cmbchan_mode >>> +Date:        October 2025 >>> +KernelVersion:    6.19 >>> +Contact:    Jinlong Mao , Tao Zhang >>> , Jie Gan >>> +Description: >>> +        (RW) Configure the CMB/MCMB channel mode for all enabled ports. >>> +        Value 0 means raw channel mapping mode. Value 1 means >>> channel pair marking mode. >>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >>> hwtracing/coresight/coresight-tpda.c >>> index 333b3cb23685..a9a27bcc65a1 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tpda.c >>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >>> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct >>> tpda_drvdata *drvdata) >>>       u32 val; >>>       val = readl_relaxed(drvdata->base + TPDA_CR); >>> +    val &= ~TPDA_CR_MID; >>>       val &= ~TPDA_CR_ATID; >> >> See, below. >> >>>       val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); >>> +    if (drvdata->trig_async) >>> +        val |= TPDA_CR_SRIE; >>> +    else >>> +        val &= ~TPDA_CR_SRIE; >>> +    if (drvdata->trig_flag_ts) >>> +        val |= TPDA_CR_FLRIE; >>> +    else >>> +        val &= ~TPDA_CR_FLRIE; >>> +    if (drvdata->trig_freq) >>> +        val |= TPDA_CR_FRIE; >>> +    else >>> +        val &= ~TPDA_CR_FRIE; >>> +    if (drvdata->freq_ts) >>> +        val |= TPDA_CR_FREQTS; >>> +    else >>> +        val &= ~TPDA_CR_FREQTS; >>> +    if (drvdata->cmbchan_mode) >>> +        val |= TPDA_CR_CMBCHANMODE; >>> +    else >>> +        val &= ~TPDA_CR_CMBCHANMODE; >> >> Could we clear all of the bits that are configurable in one go in the >> beginning and set the appropriate ones based on the setting ? i.e.: >> >> Do we really need to retain any values ? And if not, why not start >> with a fresh set of values and avoid the read ? >> >>>       writel_relaxed(val, drvdata->base + TPDA_CR); >>> + >>> +    /* >>> +     * If FLRIE bit is set, set the master and channel >>> +     * id as zero >>> +     */ >>> +    if (drvdata->trig_flag_ts) >>> +        writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >>>   } >>>   static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >>> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = { >>>       .link_ops    = &tpda_link_ops, >>>   }; >>> +static ssize_t trig_async_enable_show(struct device *dev, >>> +                      struct device_attribute *attr, >>> +                      char *buf) >>> +{ >>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + >>> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); >>> +} >>> + >>> +static ssize_t trig_async_enable_store(struct device *dev, >>> +                       struct device_attribute *attr, >>> +                       const char *buf, >>> +                       size_t size) >>> +{ >>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> +    unsigned long val; >>> + >>> +    if (kstrtoul(buf, 0, &val)) >>> +        return -EINVAL; >>> + >>> +    guard(spinlock)(&drvdata->spinlock); >>> +    drvdata->trig_async = !!val; >>> + >> >> >> >>> +    return size; >>> +} >>> +static DEVICE_ATTR_RW(trig_async_enable); >> >> ... >> >>> +static DEVICE_ATTR_RW(trig_flag_ts_enable); >> >> ... >> >>> +static DEVICE_ATTR_RW(trig_freq_enable); >> >> ... >>> +static DEVICE_ATTR_RW(freq_ts_enable); >> >> These attribute are boolean and looks like we could save some space on >> code by using dev_ext_attribute. >> see tpdm_simple_dataset_rw()/tpdm_simple_dataset_ro() . You could >> >> #define TPDA_TRIG_ASYNC        0 >> #define TPDA_TRIG_FLAG_TS     1 >> #define TPDA_TRIG_FREQ        2 >> >> >> tpda_trig_sysfs_show/store() >> >>   bool *ptr; >>   switch (eattr->var) { >>   case TPDA_TRIG_ASYNC: >>      ptr = &drvdata->trig_async; >>      break; >>   case TPDA_TRIG_FLAG_TS: >>      ptr = &drvdata->trig_flag_ts; >>      break; >> ... >> >>   } >> >> >> > > -->8-- > > Cut here > >>> + >>> +static ssize_t global_flush_req_show(struct device *dev, >>> +                     struct device_attribute *attr, >>> +                     char *buf) >>> +{ >>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> +    unsigned long val; >>> + >>> +    if (!drvdata->csdev->refcnt) >>> +        return -EINVAL; >>> + >>> +    guard(spinlock)(&drvdata->spinlock); >>> +    CS_UNLOCK(drvdata->base); >>> +    val = readl_relaxed(drvdata->base + TPDA_CR); >>> +    CS_LOCK(drvdata->base); >>> +    /* Only read value for bit 0 */ >>> +    val &= BIT(0); >>> + >>> +    return sysfs_emit(buf, "%lu\n", val); >>> +} >>> + >>> +static ssize_t global_flush_req_store(struct device *dev, >>> +                      struct device_attribute *attr, >>> +                      const char *buf, >>> +                      size_t size) >>> +{ >>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> +    unsigned long val; >>> + >>> +    if (kstrtoul(buf, 0, &val)) >>> +        return -EINVAL; >>> + >>> +    if (!drvdata->csdev->refcnt || !val) >>> +        return -EINVAL; >>> + >>> +    guard(spinlock)(&drvdata->spinlock); >>> +    CS_UNLOCK(drvdata->base); >>> +    val = readl_relaxed(drvdata->base + TPDA_CR); >>> +    /* Only set bit 0 */ >>> +    val |= BIT(0); >> >> What is BIT 0 ? Please document it >> >>> +    writel_relaxed(val, drvdata->base + TPDA_CR); >>> +    CS_LOCK(drvdata->base); >>> + >>> +    return size; >>> +} > > Also this, global_flush_req seems to be a separate change from the rest > of the additions in the patch. Why not split it into a separate patch > with appropriate description of what this is for ? Hi Suzuki, global_flush_req is part of the TPDA_CR register, it's the bit0 of the register. I should document it in header file: /* Cross trigger Global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) We also have below bit that is not in use: #define TPDA_CR_FREQREQ BIT(1) It's frequency request bit, that determines the frequency for generating frequency packets. Thanks, Jie > > Suzuki