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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c1e7c147943sm2039789a12.26.2025.12.19.04.19.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Dec 2025 04:19:37 -0800 (PST) Message-ID: <832fb36e-35e4-4c73-b32c-ee77489db951@oss.qualcomm.com> Date: Fri, 19 Dec 2025 20:19:30 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tao Zhang References: <20251219-add_sysfs_nodes_to_configure_tpda-v5-0-ca93ddfe9d30@oss.qualcomm.com> <20251219-add_sysfs_nodes_to_configure_tpda-v5-1-ca93ddfe9d30@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 6Upss6lZXI7tHiWsAz_BvCzGBnpkAFMr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDEwMiBTYWx0ZWRfX/KF8hkoytLwa QPb2LWCdPb6JBrVfRV3T8xMHIIWyvgcRmiA3y65NNHj5UlBUiDPwz1kSclxewlh/cWg0y/rBM0H wuByaMjwodhhnuJReH+fZeH9XJa7PsB5J/MQqPRJZZoFQnK6zUtCLvJG+sHvR7LhHqLVJ3QN37C 7aZwW467T3mU+LVxFMUkyxlM71kaNc3GRf8ZvhfkT5kNcbYVL1TwqRXXIhwwiCD3GTenFE83oli shWWPbM4gLOTDP7fgduP1b3tb2/NbUN3aqaQyGdXCF0qY0fH40wapexNSOMcVMZPtaTnZ1a0CeR msUWyzyL4JtOndLXBT4sy268/Wpj2Qr+WtmonrMrTzDUFRdOl4/6ga+E7gqjJHS2wxMFiEg6EhV gs8VOBY3Nc/ko7VZ8LfZ4b8fu7ruom5dm2eDv+TVv4y1dzrmQSDxJi5uaB2V9yscGHfBSQjDYep T12i9nSppyzCRSaCRsw== X-Proofpoint-ORIG-GUID: 6Upss6lZXI7tHiWsAz_BvCzGBnpkAFMr X-Authority-Analysis: v=2.4 cv=Lp2fC3dc c=1 sm=1 tr=0 ts=694542db cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=_uz3lYCekpwsQ1Z5yrUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_03,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190102 On 12/19/2025 6:22 PM, Suzuki K Poulose wrote: > On 19/12/2025 10:04, Jie Gan wrote: >> From: Tao Zhang >> >> Introduce sysfs nodes to configure cross-trigger parameters for TPDA. >> These registers define the characteristics of cross-trigger packets, >> including generation frequency and flag values. >> >> Signed-off-by: Tao Zhang >> Reviewed-by: James Clark >> Co-developed-by: Jie Gan >> Signed-off-by: Jie Gan >> --- >>   .../ABI/testing/sysfs-bus-coresight-devices-tpda   |  43 +++++++ >>   drivers/hwtracing/coresight/coresight-tpda.c       | 138 +++++++++++ >> +++++++++- >>   drivers/hwtracing/coresight/coresight-tpda.h       |  69 ++++++++++- >>   3 files changed, 243 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> new file mode 100644 >> index 000000000000..a7855922328e >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> @@ -0,0 +1,43 @@ >> +What:        /sys/bus/coresight/devices//global_cr/ >> trig_async_enable >> +Date:        December 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger synchronization sequence >> interface. >> + >> +What:        /sys/bus/coresight/devices//global_cr/ >> trig_flag_ts_enable >> +Date:        December 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger FLAG packet request interface. >> + >> +What:        /sys/bus/coresight/devices//global_cr/ >> trig_freq_enable >> +Date:        December 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger FREQ packet request interface. >> + >> +What:        /sys/bus/coresight/devices//global_cr/ >> freq_ts_enable >> +Date:        December 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable the timestamp for all FREQ packets. >> + >> +What:        /sys/bus/coresight/devices//global_cr/ >> global_flush_req >> +Date:        December 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Set global (all ports) flush request bit. The bit >> remains set until a >> +        global flush request sequence completes. >> + >> +What:        /sys/bus/coresight/devices//global_cr/ >> cmbchan_mode >> +Date:        December 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Configure the CMB/MCMB channel mode for all enabled ports. >> +        Value 0 means raw channel mapping mode. Value 1 means channel >> pair marking mode. >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >> hwtracing/coresight/coresight-tpda.c >> index 3a3825d27f86..d25a8bcfb3d4 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.c >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >> @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct >> tpda_drvdata *drvdata, >>   /* Settings pre enabling port control register */ >>   static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) >>   { >> -    u32 val; >> +    u32 val = 0; >> -    val = readl_relaxed(drvdata->base + TPDA_CR); >> -    val &= ~TPDA_CR_ATID; >>       val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); >> +    if (drvdata->trig_async) >> +        val |= TPDA_CR_SRIE; >> + >> +    if (drvdata->trig_flag_ts) >> +        val |= TPDA_CR_FLRIE; >> + >> +    if (drvdata->trig_freq) >> +        val |= TPDA_CR_FRIE; >> + >> +    if (drvdata->freq_ts) >> +        val |= TPDA_CR_FREQTS; >> + >> +    if (drvdata->cmbchan_mode) >> +        val |= TPDA_CR_CMBCHANMODE; >> + >>       writel_relaxed(val, drvdata->base + TPDA_CR); >> + >> +    /* >> +     * If FLRIE bit is set, set the master and channel >> +     * id as zero >> +     */ >> +    if (drvdata->trig_flag_ts) >> +        writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >>   } >>   static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >> @@ -258,6 +278,116 @@ static const struct coresight_ops tpda_cs_ops = { >>       .link_ops    = &tpda_link_ops, >>   }; >> +/* Read cross-trigger register member */ >> +static ssize_t tpda_trig_sysfs_show(struct device *dev, >> +                    struct device_attribute *attr, >> +                    char *buf) >> +{ >> +    struct tpda_trig_sysfs_attribute *tpda_attr = >> +        container_of(attr, struct tpda_trig_sysfs_attribute, attr); >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    switch (tpda_attr->mem) { >> +    case FLREQ: >> +        if (!drvdata->csdev->refcnt) >> +            return -EINVAL; >> + >> +        val = readl_relaxed(drvdata->base + TPDA_CR); >> +        /* read global flush request bit only */ >> +        val &= TPDA_CR_FLREQ; >> +        return sysfs_emit(buf, "%lu\n", val); >> +    case FREQTS: >> +        return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); >> +    case FRIE: >> +        return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >trig_freq); >> +    case FLRIE: >> +        return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >trig_flag_ts); >> +    case SRIE: >> +        return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >trig_async); >> +    case CMBCHANMODE: >> +        return sysfs_emit(buf, "%u\n", (unsigned int)drvdata- >> >cmbchan_mode); >> + >> +    } >> +    return -EINVAL; >> +} >> + >> +static ssize_t tpda_trig_sysfs_store(struct device *dev, >> +                     struct device_attribute *attr, >> +                     const char *buf, >> +                     size_t size) >> +{ >> +    struct tpda_trig_sysfs_attribute *tpda_attr = >> +        container_of(attr, struct tpda_trig_sysfs_attribute, attr); >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    ssize_t ret = -EINVAL; >   +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return ret; > >         return -EINVAL; > >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    switch (tpda_attr->mem) { >> +    case FLREQ: >> +        if (!drvdata->csdev->refcnt || !val) >> +            return ret; >             return -EINVAL; > >> + >> +        val = readl_relaxed(drvdata->base + TPDA_CR); > > CS_UNLOCK before readl ? I didn't mean the global_flush_req to be > unified with the rest. Obviously it has different access semantics. We dont need CS_UNLOCK for reading a register. The global_flush_req is supposing access when the tpda is enabled. I will put it in a separate patch with detail description. > > >> +        /* set global flush request bit */ >> +        val |= TPDA_CR_FLREQ; >> +        CS_UNLOCK(drvdata->base); >> +        writel_relaxed(val, drvdata->base + TPDA_CR); >> +        CS_LOCK(drvdata->base); >> +        ret = size; > > Please remove this from all the cases and explicitly return -EINVAL in > the error cases. Will fix it. > >> +        break; >> +    case FREQTS: >> +        drvdata->freq_ts = !!val; >> +        ret = size; >> +        break; >> +    case FRIE: >> +        drvdata->trig_freq = !!val; >> +        ret = size; >> +        break; >> +    case FLRIE: >> +        drvdata->trig_flag_ts = !!val; >> +        ret = size; >> +        break; >> +    case SRIE: >> +        drvdata->trig_async = !!val; >> +        ret = size; >> +        break; >> +    case CMBCHANMODE: >> +        drvdata->cmbchan_mode = !!val; >> +        ret = size; >> +        break; >> +    default: >         return -EINVAL; > >> +        break; >> +    } >> + > > >> +    return ret; > >     return size; > >> +} >> + >> +static struct attribute *tpda_global_cr_attrs[] = { >> +    tpda_trig_sysfs_rw(global_flush_req, FLREQ), >> +    tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), >> +    tpda_trig_sysfs_rw(trig_freq_enable, FRIE), >> +    tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), >> +    tpda_trig_sysfs_rw(trig_async_enable, SRIE), >> +    tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), >> +    NULL, >> +}; >> + >> +static struct attribute_group tpda_global_cr_attr_grp = { >> +    .attrs    = tpda_global_cr_attrs, >> +    .name    = "global_cr", >> +}; >> + >> +static const struct attribute_group *tpda_attr_grps[] = { >> +    &tpda_global_cr_attr_grp, >> +    NULL, >> +}; >> + >>   static int tpda_init_default_data(struct tpda_drvdata *drvdata) >>   { >>       int atid; >> @@ -273,6 +403,7 @@ static int tpda_init_default_data(struct >> tpda_drvdata *drvdata) >>           return atid; >>       drvdata->atid = atid; >> +    drvdata->freq_ts = true; >>       return 0; >>   } >> @@ -316,6 +447,7 @@ static int tpda_probe(struct amba_device *adev, >> const struct amba_id *id) >>       desc.ops = &tpda_cs_ops; >>       desc.pdata = adev->dev.platform_data; >>       desc.dev = &adev->dev; >> +    desc.groups = tpda_attr_grps; >>       desc.access = CSDEV_ACCESS_IOMEM(base); >>       drvdata->csdev = coresight_register(&desc); >>       if (IS_ERR(drvdata->csdev)) >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >> hwtracing/coresight/coresight-tpda.h >> index c6af3d2da3ef..8a075cfbc3cc 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.h >> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >> @@ -1,6 +1,6 @@ >>   /* SPDX-License-Identifier: GPL-2.0 */ >>   /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights >> reserved. >> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All >> rights reserved. >>    */ >>   #ifndef _CORESIGHT_CORESIGHT_TPDA_H >> @@ -8,6 +8,30 @@ >>   #define TPDA_CR            (0x000) >>   #define TPDA_Pn_CR(n)        (0x004 + (n * 4)) >> +#define TPDA_FPID_CR        (0x084) >> + >> +/* Cross trigger Global (all ports) flush request bit */ >> +#define TPDA_CR_FLREQ        BIT(0) >> +/* Cross trigger FREQ packets timestamp bit */ >> +#define TPDA_CR_FREQTS        BIT(2) >> +/* Cross trigger FREQ packet request bit */ >> +#define TPDA_CR_FRIE        BIT(3) >> +/* Cross trigger FLAG packet request interface bit */ >> +#define TPDA_CR_FLRIE        BIT(4) >> +/* Cross trigger synchronization bit */ >> +#define TPDA_CR_SRIE        BIT(5) >> +/* Bits 6 ~ 12 is for atid value */ >> +#define TPDA_CR_ATID        GENMASK(12, 6) >> +/* Bits 13 ~ 19 is for mid value */ >> +/* Assign a unique master ID to identify the TPDA device */ >> +#define TPDA_CR_MID        GENMASK(19, 13) > > Where do we use this ? Does this need to be preserved ? > Is this programmable ? > We havent usage of this field. I will remove it in next version. Thanks, Jie > Suzuki > >> +/* >> + * Channel mode bit of the packetization of CMB/MCB traffic >> + * 0 - raw channel mapping mode >> + * 1 - channel pair marking mode >> + */ >> +#define TPDA_CR_CMBCHANMODE    BIT(20) >> + >>   /* Aggregator port enable bit */ >>   #define TPDA_Pn_CR_ENA        BIT(0) >>   /* Aggregator port CMB data set element size bit */ >> @@ -17,9 +41,6 @@ >>   #define TPDA_MAX_INPORTS    32 >> -/* Bits 6 ~ 12 is for atid value */ >> -#define TPDA_CR_ATID        GENMASK(12, 6) >> - >>   /** >>    * struct tpda_drvdata - specifics associated to an TPDA component >>    * @base:       memory mapped base address for this component. >> @@ -29,6 +50,11 @@ >>    * @enable:     enable status of the component. >>    * @dsb_esize   Record the DSB element size. >>    * @cmb_esize   Record the CMB element size. >> + * @trig_async:    Enable/disable cross trigger synchronization >> sequence interface. >> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request >> interface. >> + * @trig_freq:    Enable/disable cross trigger FREQ packet request >> interface. >> + * @freq_ts:    Enable/disable the timestamp for all FREQ packets. >> + * @cmbchan_mode: Configure the CMB/MCMB channel mode. >>    */ >>   struct tpda_drvdata { >>       void __iomem        *base; >> @@ -38,6 +64,41 @@ struct tpda_drvdata { >>       u8            atid; >>       u32            dsb_esize; >>       u32            cmb_esize; >> +    bool            trig_async; >> +    bool            trig_flag_ts; >> +    bool            trig_freq; >> +    bool            freq_ts; >> +    bool            cmbchan_mode; >> +}; >> + >> +/* Enumerate members of global control register(cr) */ >> +enum tpda_cr_mem { >> +    FLREQ, >> +    FREQTS, >> +    FRIE, >> +    FLRIE, >> +    SRIE, >> +    CMBCHANMODE >> +}; >> + >> +/** >> + * struct tpda_trig_sysfs_attribute - Record the member variables of >> cross >> + * trigger register that need to be operated by sysfs file >> + * @attr:    The device attribute >> + * @mem:    The member in the control register data structure >> + */ >> +struct tpda_trig_sysfs_attribute { >> +    struct device_attribute attr; >> +    enum tpda_cr_mem mem; >>   }; >> +#define tpda_trig_sysfs_rw(name, mem)                \ >> +    (&((struct tpda_trig_sysfs_attribute[]) {        \ >> +       {                            \ >> +        __ATTR(name, 0644, tpda_trig_sysfs_show,    \ >> +        tpda_trig_sysfs_store),                \ >> +        mem,                        \ >> +       }                            \ >> +       })[0].attr.attr) >> + >>   #endif  /* _CORESIGHT_CORESIGHT_TPDA_H */ >> >