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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN3PEPF0000B371.mail.protection.outlook.com (10.167.243.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.0 via Frontend Transport; Sat, 29 Aug 2026 03:40:51 +0000 Received: from purico-9dcchost.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Fri, 28 Aug 2026 22:40:50 -0500 From: Melody Wang To: CC: LKML , Tom Lendacky , Melody Wang Subject: [PATCH v1 4/8] x86/sev: Route unsupported APIC register accesses to the hypervisor APIC emulation Date: Sat, 29 Aug 2026 03:39:42 +0000 Message-ID: <836a4e242279aacaa58ede597eeaf2ac6074f562.1787973545.git.huibo.wang@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B371:EE_|MN0PR12MB5714:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c0fe551-6f8a-45dc-1132-08df057f5261 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|82310400026|1800799024|36860700016|22082099003|11063799006|18002099003|56012099006|3023799007|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jKMqJzr3RYJ/0EElkf1hKZ4BDrwWUtXw7dr2ie8gpv8nTd3nLNLWax7/UTqNwbMQiqU0lfr3/va2VQMmXpRCaKFZe4AS/Ei86yDcpXCdRc9kAb/ICNKqlNIDcgSToIt2gixMJOfp4lbqWCqEs4qX5w9fhdA9m338K1e5Brabnw/UXPk2Xfo2oEfLvjxC9dVl2VRqIIffP8MzlODFMU4OPUnbpVnenpNYgdnhuseKpIkRCun+csUwoyaUBomll38wbkKhmehSPadtX3Jkrti8muRQVZ9VRqKoUTpyebI/MNkBozK338AcVvUdrm8FNBp+KVDXRZ2ts9rrQZar/SsGMobVQIUADWyDq7CsZyoZhzDMmyEKtYPuYoof39bQ0rb4LxHuFnLsrvgZFHT5aLPkBHiARwLDCNRkELD/SEnS9L7dDaI6qTdgqG47PPClfpd0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2026 03:40:51.0561 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c0fe551-6f8a-45dc-1132-08df057f5261 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B371.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5714 The SVSM APIC emulation supports only a subset of the X2APIC MSRs. Right now only basic APIC functionality related to interrupt delivery is supported. Therefore, route the unsupported ones to the hypervisor's X2APIC emulation. Signed-off-by: Melody Wang --- arch/x86/coco/sev/core.c | 12 ++++++------ arch/x86/include/asm/sev-common.h | 1 + arch/x86/include/asm/sev.h | 8 ++++---- arch/x86/kernel/apic/x2apic_savic.c | 8 ++++---- arch/x86/kernel/apic/x2apic_svsm.c | 9 ++++++--- 5 files changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index c54269366278..ec8fc02bd636 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -972,7 +972,7 @@ int __init sev_es_efi_map_ghcbs_cas(pgd_t *pgd) return 0; } -u64 savic_ghcb_msr_read(u32 reg) +u64 sev_apic_ghcb_msr_read(u32 reg) { u64 msr = APIC_BASE_MSR + (reg >> 4); struct pt_regs regs = { .cx = msr }; @@ -988,9 +988,9 @@ u64 savic_ghcb_msr_read(u32 reg) res = __vc_handle_msr(ghcb, &ctxt, false); if (res != ES_OK) { - pr_err("Secure AVIC MSR (0x%llx) read returned error (%d)\n", msr, res); + pr_err("APIC MSR via GHCB (0x%llx) read returned error (%d)\n", msr, res); /* MSR read failures are treated as fatal errors */ - sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_SAVIC_FAIL); + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_APIC_MSR_FAIL); } __sev_put_ghcb(&state); @@ -998,7 +998,7 @@ u64 savic_ghcb_msr_read(u32 reg) return regs.ax | regs.dx << 32; } -void savic_ghcb_msr_write(u32 reg, u64 value) +void sev_apic_ghcb_msr_write(u32 reg, u64 value) { u64 msr = APIC_BASE_MSR + (reg >> 4); struct pt_regs regs = { @@ -1018,9 +1018,9 @@ void savic_ghcb_msr_write(u32 reg, u64 value) res = __vc_handle_msr(ghcb, &ctxt, true); if (res != ES_OK) { - pr_err("Secure AVIC MSR (0x%llx) write returned error (%d)\n", msr, res); + pr_err("APIC MSR via GHCB (0x%llx) write returned error (%d)\n", msr, res); /* MSR writes should never fail. Any failure is fatal error for SNP guest */ - sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_SAVIC_FAIL); + sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_APIC_MSR_FAIL); } __sev_put_ghcb(&state); diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 095fbafe8a2c..585ddc44b6b4 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -210,6 +210,7 @@ struct snp_psc_desc { #define GHCB_TERM_SVSM_CA_REMAP_FAIL 11 /* SVSM is present but CA could not be remapped */ #define GHCB_TERM_SAVIC_FAIL 12 /* Secure AVIC-specific failure */ #define GHCB_TERM_ALT_INJ_FAIL 13 /* Alternate Injection-specific failure */ +#define GHCB_TERM_APIC_MSR_FAIL 14 /* APIC MSR failure */ #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 557c4d1ef4be..3cb6c5d6a6e0 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -541,8 +541,8 @@ void __init snp_secure_tsc_prepare(void); void __init snp_secure_tsc_init(void); enum es_result savic_register_gpa(u64 gpa); enum es_result savic_unregister_gpa(u64 *gpa); -u64 savic_ghcb_msr_read(u32 reg); -void savic_ghcb_msr_write(u32 reg, u64 value); +u64 sev_apic_ghcb_msr_read(u32 reg); +void sev_apic_ghcb_msr_write(u32 reg, u64 value); static __always_inline void vc_ghcb_invalidate(struct ghcb *ghcb) { @@ -650,8 +650,8 @@ static inline void __init snp_secure_tsc_init(void) { } static inline void sev_evict_cache(void *va, int npages) {} static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUPPORTED; } static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UNSUPPORTED; } -static inline void savic_ghcb_msr_write(u32 reg, u64 value) { } -static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; } +static inline void sev_apic_ghcb_msr_write(u32 reg, u64 value) { } +static inline u64 sev_apic_ghcb_msr_read(u32 reg) { return 0; } #endif /* CONFIG_AMD_MEM_ENCRYPT */ diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c index 4bc6d7e018a5..990e4a379e07 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -72,7 +72,7 @@ static u32 savic_read(u32 reg) case APIC_LVT0: case APIC_LVT1: case APIC_LVTERR: - return savic_ghcb_msr_read(reg); + return sev_apic_ghcb_msr_read(reg); case APIC_ID: case APIC_LVR: case APIC_TASKPRI: @@ -193,7 +193,7 @@ static void savic_icr_write(u32 icr_low, u32 icr_high) icr_data = ((u64)icr_high) << 32 | icr_low; if (dsh != APIC_DEST_SELF) - savic_ghcb_msr_write(APIC_ICR, icr_data); + sev_apic_ghcb_msr_write(APIC_ICR, icr_data); apic_set_reg64(this_cpu_ptr(savic_page), APIC_ICR, icr_data); } @@ -210,7 +210,7 @@ static void savic_write(u32 reg, u32 data) case APIC_LVTTHMR: case APIC_LVTPC: case APIC_LVTERR: - savic_ghcb_msr_write(reg, data); + sev_apic_ghcb_msr_write(reg, data); break; case APIC_TASKPRI: case APIC_EOI: @@ -316,7 +316,7 @@ static void savic_eoi(void) * interrupts. Return to the guest from GHCB protocol event takes * care of re-evaluating interrupt state. */ - savic_ghcb_msr_write(APIC_EOI, 0); + sev_apic_ghcb_msr_write(APIC_EOI, 0); } else { /* * Hardware clears APIC_ISR and re-evaluates the interrupt state diff --git a/arch/x86/kernel/apic/x2apic_svsm.c b/arch/x86/kernel/apic/x2apic_svsm.c index b553bfde4b85..1a1aefc26726 100644 --- a/arch/x86/kernel/apic/x2apic_svsm.c +++ b/arch/x86/kernel/apic/x2apic_svsm.c @@ -69,14 +69,17 @@ static u32 __svsm_apic_msr_rw(u32 reg, u32 v, bool write) call.rdx = v; ret = svsm_perform_call_protocol(&call); - if (ret) { + if (ret) { pr_err("%s: 0x%x, error: %d\n", call_reg_str, reg, ret); sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_ALT_INJ_FAIL); } break; default: - pr_err("%s 0x%x not supported\n", call_reg_str, reg); - return 0; + if (write) { + sev_apic_ghcb_msr_write(reg, v); + } else { + return sev_apic_ghcb_msr_read(reg); + } } return call.rdx_out; -- 2.43.0