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Thu, 24 Jul 2025 11:48:40 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56OBmdZK031545 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Jul 2025 11:48:39 GMT Received: from [10.216.46.74] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 24 Jul 2025 04:48:32 -0700 Message-ID: <836d6ead-6620-4bc7-8dc1-d9220e7c83dc@quicinc.com> Date: Thu, 24 Jul 2025 17:18:27 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 2/4] dt-bindings: mmc: controller: Add max-sd-hs-frequency property Content-Language: en-US To: Krzysztof Kozlowski , Konrad Dybcio , Ulf Hansson , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Bjorn Andersson , "Konrad Dybcio" , Adrian Hunter CC: , , , , , , , , , , , References: <20250618072818.1667097-1-quic_sartgarg@quicinc.com> <20250618072818.1667097-3-quic_sartgarg@quicinc.com> <6040afd9-a2a8-49f0-85e9-95257b938156@kernel.org> <9627ed6f-2bb8-40b0-b647-5f659d87f2f9@oss.qualcomm.com> <5bdae07b-a7b1-49be-b843-1704981bc63b@oss.qualcomm.com> <83f88dd5-8c74-4c2f-b94e-6c16dcbd44f1@kernel.org> From: Sarthak Garg In-Reply-To: <83f88dd5-8c74-4c2f-b94e-6c16dcbd44f1@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI0MDA4OSBTYWx0ZWRfX7T0LjmLcGy7c +swmliuZYqIIKDHWJvzH4FK1TVK79xgzJzuS5tLuHsLC3RJE79DbXzk4bPj+cPP5vWU2nkFY+1M he0p6e9GnhnigTuYF9K/I3l2Js/Gxop/9xhScp2ChyaF5B2jBIQ/qPQv0nFcwhtSrVp3JXhG6A3 jag79ikSR2vJFkCuNLo2ys6To4o41ebVHQpJP50NtnUoH3sNmBhCxFUkIv7/Tvyf6Oa3UBDJ/8R D8G1aRjhCkZJGyCJ18UQdN7rcHUNr9qObIvuEx73R3tBJy5j/G8smLd2AUauYTpC+Blc0bVXbCp cv1qz6zf1F+YfYbX9qsi3HPpFhdwbyprgGXnFc17V4NDIyg4Dji/EgzI/qVOLqITdc82wAuX03H 4DUqAR8w89A2DHPc56EAD9yZz9N4ZjP4Q5zchHqOTfQFoMapdOiAkTqHU8ezuvwSDc5WHBeN X-Proofpoint-ORIG-GUID: _sbB_5csx5GOa3_s-XTZsmkiq3wWTN4j X-Proofpoint-GUID: _sbB_5csx5GOa3_s-XTZsmkiq3wWTN4j X-Authority-Analysis: v=2.4 cv=C/TpyRP+ c=1 sm=1 tr=0 ts=68821d98 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=k1EdMiZ1uo5d-mV4pycA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-24_01,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 mlxscore=0 clxscore=1011 impostorscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507240089 On 7/1/2025 3:00 PM, Krzysztof Kozlowski wrote: > On 01/07/2025 11:04, Konrad Dybcio wrote: >>>>>> >>>>>> Looking at the docs, a number of platforms have various limitations >>>>>> with regards to frequency at specific speed-modes, some of which seem >>>>>> to be handled implicitly by rounding in the clock framework's >>>>>> round/set_rate(). >>>>>> >>>>>> I can very easily imagine there are either boards or platforms in the >>>>>> wild, where the speed must be limited for various reasons, maybe some >>>>>> of them currently don't advertise it (like sm8550 on next/master) to >>>>>> hide that >>>>> >>>>> But there are no such now. The only argument (fact) provided in this >>>>> patchset is: this is issue specific to SM8550 SoC, not the board. See >>>>> last patch. Therefore this is compatible-deducible and this makes >>>>> property without any upstream user. >>>> >>>> When one appears, we will have to carry code to repeat what the property >>>> does, based on a specific compatible.. And all OS implementations will >>>> have to do the same, instead of parsing the explicit information >>> >>> Adding new property in such case will be trivial and simple, unlike >>> having to maintain unused ABI. >>> >>> And it will be unused, because last patch DTS should be rejected on that >>> basis: adding redundant properties which are already defined by the >>> compatible. >> >> Got some more fresh information.. This apparently *does* vary across >> boards, as there is a recommended hardware workaround to this rate >> limitation (requiring an external clock source, which is up to the >> OEM to implement or not) > > > This should be clearly explained in commit msg and the DTS patch > re-written because it seems it is not a property of the SoC. > > I mean, really, that last patch here makes entire discussion pointless, > because till it is in the patchset is a proof this is a SoC level property. > > Best regards, > Krzysztof Sure I'll update the commit message clearly mentioning it as board specific and update the DTS patch and have these changes in board specific dts files (for e.g sm8550-mtp.dts). As rightly stated above this configuration will vary across boards as well. Regards, Sarthak