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X-CSE-ConnectionGUID: Lm5ESs1uRje2v3vUil3Pbw== X-CSE-MsgGUID: Nmy7KQwYQwSUUrrncwj4Qw== X-IronPort-AV: E=McAfee;i="6700,10204,11245"; a="29801130" X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="29801130" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2024 22:38:24 -0800 X-CSE-ConnectionGUID: 3u7azeIwSYCzt9aSZon4Rw== X-CSE-MsgGUID: XYoWjP+nSS+br4byYIhU6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="114348431" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO [10.0.2.15]) ([10.246.16.81]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2024 22:38:19 -0800 Message-ID: <8383c639-66ce-4252-b3e8-734cb6688b44@intel.com> Date: Mon, 4 Nov 2024 08:38:14 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset To: Josua Mayer , Haibo Chen , Ulf Hansson , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Mikhail Anikin , Jon Nettleton , Yazan Shhady , Rabeeh Khoury , imx@lists.linux.dev, linux-mmc@vger.kernel.org, s32@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20241101-imx-emmc-reset-v3-0-184965eed476@solid-run.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20241101-imx-emmc-reset-v3-0-184965eed476@solid-run.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/11/24 13:42, Josua Mayer wrote: > Signed-off-by: Josua Mayer > --- > Changes in v3: > - reused existing control register definition from sdhci-esdhc.h > (Reported-by: Bough Chen ) > - placed both control register mask definitions next to each other > - fixed timeout write register name > - Link to v2: https://lore.kernel.org/r/20241030-imx-emmc-reset-v2-0-b3a823393974@solid-run.com > > Changes in v2: > - replaced udelay with usleep_range > (Reported-by: Adrian Hunter ) > - added comments for delay values > (Reported-by: Peng Fan ) > - delay values based on JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, > on page 159 > (Thanks to Bough Chen ) > - added a second patch demonstrating a cosmetic issue revealed by first > patch - it bothered me during development but is not important > - Link to v1: https://lore.kernel.org/r/20241027-imx-emmc-reset-v1-1-d5d0c672864a@solid-run.com > > --- > Josua Mayer (2): > mmc: host: sdhci-esdhc-imx: implement emmc hardware reset > mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask For both: Acked-by: Adrian Hunter