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Wed, 04 Feb 2026 09:48:40 -0800 (PST) X-Received: by 2002:a05:6a00:3e01:b0:81a:74e5:a4cf with SMTP id d2e1a72fcca58-8241c19e37dmr3356489b3a.11.1770227319922; Wed, 04 Feb 2026 09:48:39 -0800 (PST) Received: from [192.168.0.103] ([124.123.178.21]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8241d4b8c8dsm2974606b3a.69.2026.02.04.09.48.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Feb 2026 09:48:39 -0800 (PST) Message-ID: <838b9868-dd6f-4264-8947-d56f5a781946@oss.qualcomm.com> Date: Wed, 4 Feb 2026 23:18:31 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] dt-bindings: clock: qcom: Add X1P42100 video clock controller To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-purwa-videocc-camcc-v1-0-b23de57df5ba@oss.qualcomm.com> <20260128-purwa-videocc-camcc-v1-1-b23de57df5ba@oss.qualcomm.com> <82c6750d-8fa7-4837-b537-8fc6df9841a2@oss.qualcomm.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <82c6750d-8fa7-4837-b537-8fc6df9841a2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA0MDEzNSBTYWx0ZWRfX31w1eB/tXrVn xoGsF87oCqCZ7gID4ea7FatLuDVRbKa1wlZYla6rhbPTvwrmLXU7LofKg1s+1sRdXmudoOazxcI B5UP4s9zS4iHZZDupfGQiSje4EmIYlWLPhxGHO2wgWaookQb4BvxyQoIGv/+xFJnSmwDKlRnNmP p/1WuqakeVSG6I+uTQ0ORWGzYs99WT1p7nO9ugeK/qCGc62BPrA/0OxQobHy9jbgoqzRvTVkcRc wju393Kv6CCArFO+holsfjIaXCrbXxOEUFnq4u/2qFl+m6JTmQHap2S4eLFLosVmZQ8NwM0PZOF TfOlyG67qERDBw0iDdwb5Ry7ttOmexTcHWN2JTtMIXwJ7io5XL7YjO58ZVma2xv0DbxwHnRtJ+t 1R9L6wvpcUVGKcwaLgFfS6zUlKENO/j/JmPDUF7lgqZ+D+Y+r4trXtkLAGeakajn+TUGho402h2 LYV/yxFGf1bD4CGzuhw== X-Authority-Analysis: v=2.4 cv=DLmCIiNb c=1 sm=1 tr=0 ts=69838679 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=2H5/5ZkxJs/wMzWGxXwROQ==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BjO1pcXgz56rAAoD9qIA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: XDl5efEYGP6-V9L368FZdcDSnB34vbAk X-Proofpoint-ORIG-GUID: XDl5efEYGP6-V9L368FZdcDSnB34vbAk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-04_06,2026-02-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602040135 On 1/28/2026 3:38 PM, Konrad Dybcio wrote: > On 1/27/26 8:26 PM, Jagadeesh Kona wrote: >> X1P42100 video clock controller has most clocks same as SM8650, >> but it also has few additional clocks and resets. Add device >> tree bindings for the video clock controller on Qualcomm >> X1P42100 platform by defining these additional clocks and resets >> on top of SM8650. >> >> Signed-off-by: Jagadeesh Kona >> --- > > [...] > >> +#include "qcom,sm8650-videocc.h" >> + >> +/* X1P42100 introduces below new clocks and resets compared to SM8650 */ >> + >> +/* VIDEO_CC clocks */ >> +#define VIDEO_CC_MVS0_BSE_CLK 17 >> +#define VIDEO_CC_MVS0_BSE_CLK_SRC 18 >> +#define VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC 19 > > I checked a number of platforms and the _BSE clocks are only present on > Purwa, without any explanation in the corresponding docs. > > What are they used for? > These clocks are used to drive Bin stream engine, which is a sub-block of video codec HW, which seems to be present only on Purwa. Thanks, Jagadeesh