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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3f2fe67f96sm8032266a12.13.2025.07.22.22.10.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Jul 2025 22:10:06 -0700 (PDT) Message-ID: <838c6cda-6128-4fd5-a541-d71caee6c107@oss.qualcomm.com> Date: Wed, 23 Jul 2025 13:10:01 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function for byte-cntr To: Mike Leach , Jie Gan Cc: Suzuki K Poulose , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin , Tingwei Zhang , Yuanfang Zhang , Mao Jinlong , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20250714063109.591-1-jie.gan@oss.qualcomm.com> <20250714063109.591-9-jie.gan@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA0MSBTYWx0ZWRfX6kPBdNMm4n4t MF2a5Dd+c1X/R+Sa5B0oA6vc5eryKOlS7sDSe1jjDsmN5uOyTuGxwh4qW/sTMPXsQiHewafMkOu qtO27j71wo+akf2etkdBZ+roccKe8VVeD1mlSVljrvsHE58i8+cTrH+ymUF8ONxOdMB5syvTUMu 6FuQRlAjQyr1SWp5JlvBP5TRaOhkjyaeWYwAu716nlqbrvy4esAcWseHDTw+DPJ33wYe9Ie7BDX e4bKoGi6sk6xyxdVblythmVAZA6Vr5Epo3h/+WiojeOQGxHXr2Kbv2Lv7+oyxJnKEgPWg5zSb8t zv2QANJqo9pC6drquZLNEnd61EVCXlHQTFhlun68vvxgHDQE9N+2rtt647/Bnfgi3DB4ODZF755 nF+ZFukCsEdSDks0K60LtOIQCffC3XNApe0CsscEvYbYh/FosWclH+oZne2H3/ysBnlqAjlW X-Proofpoint-ORIG-GUID: dm2uVZSRyUfUTwqrYdLWDRVYH_Q0t8Ky X-Proofpoint-GUID: dm2uVZSRyUfUTwqrYdLWDRVYH_Q0t8Ky X-Authority-Analysis: v=2.4 cv=OPUn3TaB c=1 sm=1 tr=0 ts=68806eb0 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=RYLkNb92mBiLz5sOdEcA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_01,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 phishscore=0 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230041 On 7/22/2025 10:09 PM, Mike Leach wrote: > Hi, > > This buffer swap code looks OK in principle. The ETR is stopped, > memory synced and set to be read. > See other comments inline. > > On Mon, 14 Jul 2025 at 07:31, Jie Gan wrote: >> >> Switching the sysfs_buf when current buffer is full or the timeout is >> triggered and resets rrp and rwp registers after switched the buffer. >> Disable the ETR device if it cannot find an available buffer to switch. >> >> Signed-off-by: Jie Gan >> --- >> .../hwtracing/coresight/coresight-tmc-etr.c | 52 +++++++++++++++++++ >> 1 file changed, 52 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> index 2b73bd8074bb..3e3e1b5e78ca 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> @@ -1287,6 +1287,58 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) >> return ret ? ERR_PTR(ret) : drvdata->sysfs_buf; >> } >> >> +static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, >> + struct ctcu_byte_cntr *byte_cntr_data) >> +{ > > This entire function should be in one of the byte_cntr source files, > not in the main etr files. Please keep byte cntr code separate as far > as possible > >> + struct etr_buf_node *nd, *next, *curr_node, *picked_node; >> + struct etr_buf *curr_buf = drvdata->sysfs_buf; >> + bool found_free_buf = false; >> + >> + if (WARN_ON(!drvdata || !byte_cntr_data)) >> + return found_free_buf; >> + >> + /* Stop the ETR before we start the switching process */ >> + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) > > Can this function be called if the mode is not CS_MODE_SYSFS? > >> + __tmc_etr_disable_hw(drvdata); Hi Mike, Since I need move the whole function to byte-cntr source file, is that acceptable to export __tmc_etr_disable_hw from tmc-etr? Same with __tmc_etr_enable_hw. Thanks, Jie >> + >> + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { >> + /* curr_buf is free for next round */ >> + if (nd->sysfs_buf == curr_buf) { >> + nd->is_free = true; >> + curr_node = nd; >> + } >> + >> + if (!found_free_buf && nd->is_free && nd->sysfs_buf != curr_buf) { >> + if (nd->reading) >> + continue; >> + >> + picked_node = nd; >> + found_free_buf = true; >> + } >> + } >> + >> + if (found_free_buf) { >> + curr_node->reading = true; >> + curr_node->pos = 0; >> + drvdata->reading_node = curr_node; >> + drvdata->sysfs_buf = picked_node->sysfs_buf; >> + drvdata->etr_buf = picked_node->sysfs_buf; >> + picked_node->is_free = false; >> + /* Reset irq_cnt for next etr_buf */ >> + atomic_set(&byte_cntr_data->irq_cnt, 0); >> + /* Reset rrp and rwp when the system has switched the buffer*/ >> + CS_UNLOCK(drvdata->base); >> + tmc_write_rrp(drvdata, 0); >> + tmc_write_rwp(drvdata, 0); > > This cannot possibly be correct. RWP / RRP are pointers into the > system memory where the ETR stores data. > >> + CS_LOCK(drvdata->base); >> + /* Restart the ETR when we find a free buffer */ >> + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) >> + __tmc_etr_enable_hw(drvdata); > > What happens if the ETR is not restarted? Using __tmc_etr_disable_hw() > is correct for this use case, but if you do not restart then the extra > shutdown that would ordinarily happen in tmc_etr_disable_hw() does not > occur. How is this handled in the rest of the update? > >> + } >> + >> + return found_free_buf; >> +} >> + >> static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) >> { >> int ret = 0; >> -- >> 2.34.1 >> > > Regards > > Mike > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK