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s=20260414; d=pengutronix.de; t=1790583176; a=rsa-sha256; cv=none; b=H1b23b4oiLyJOR6i/1CwxsxzG3SiNhiMt8EoJrIGvnDPDAdSIwUs/JOIkCdPmb/vhfyW+a uncsnHI2nE9sqPoHtC2UXOpPDqIubmPs4LEgpUTSe8yvU+8BwRoMQvdHd4RexOp5L8wvHn qG84wd+g9yChw42l+Ose/sNvlP7HBwE9QSPpt45pxL2cuQeMEV10EIQ/pIzS36CJKha0at w0jglaqttll/MiIInMlyWmqXBIwdITh1Fqdl3E58iiT/nknADrgHcvmXdBdIC4Kg/NPLnK 2RJn0Y/9maIomrqboYJJANUlw1QDb5MMIV/n4BlnXU1UKCkSh0URlzAHBUHdNQ== ARC-Authentication-Results: i=1; ORIGINATING; auth=pass smtp.auth=pza@pengutronix.de smtp.mailfrom=p.zabel@pengutronix.de Message-ID: <838cc8f7099bfc5ee1cac9d3aca7a87aa7dfd17d.camel@pengutronix.de> Subject: Re: [PATCH v2 2/6] peci: controller: Add StarFive JHB100 PECI driver From: Philipp Zabel To: Changhuang Liang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Iwona Winiarska , Guenter Roeck Cc: openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-hwmon@vger.kernel.org Date: Mon, 28 Sep 2026 10:12:56 +0200 In-Reply-To: <20260928075956.62298-3-changhuang.liang@starfivetech.com> References: <20260928075956.62298-1-changhuang.liang@starfivetech.com> <20260928075956.62298-3-changhuang.liang@starfivetech.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mo, 2026-09-28 at 00:59 -0700, Changhuang Liang wrote: > Add PECI controller driver for StarFive JHB100 SoC. The driver supports > PECI protocol communication for CPU thermal management. >=20 > For this controller, the special clock and reset operation sequence is: > probe: clk_prepare_enable() then reset_control_deassert() > remove: clk_disable_unprepare() then reset_control_assert() >=20 > Co-developed-by: Mason Huo > Signed-off-by: Mason Huo > Signed-off-by: Changhuang Liang > --- > MAINTAINERS | 8 + > drivers/peci/controller/Kconfig | 17 ++ > drivers/peci/controller/Makefile | 1 + > drivers/peci/controller/peci-starfive.c | 376 ++++++++++++++++++++++++ > 4 files changed, 402 insertions(+) > create mode 100644 drivers/peci/controller/peci-starfive.c >=20 [...] > diff --git a/drivers/peci/controller/peci-starfive.c b/drivers/peci/contr= oller/peci-starfive.c > new file mode 100644 > index 000000000000..6004cb27a774 > --- /dev/null > +++ b/drivers/peci/controller/peci-starfive.c > @@ -0,0 +1,376 @@ [...] > +static int starfive_peci_init_clk_rst(struct starfive_peci *priv) > +{ > + int ret; > + > + priv->clk =3D devm_clk_get(priv->dev, NULL); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(priv->dev, PTR_ERR(priv->clk), > + "Failed to get peci clock\n"); > + > + priv->rst =3D devm_reset_control_get(priv->dev, NULL); Please use devm_reset_control_get_exclusive() directly. > + if (IS_ERR(priv->rst)) > + return dev_err_probe(priv->dev, PTR_ERR(priv->rst), > + "Failed to get reset control\n"); > + > + ret =3D clk_prepare_enable(priv->clk); > + if (ret) > + return dev_err_probe(priv->dev, ret, > + "Failed to enable peci clock\n"); > + > + ret =3D reset_control_deassert(priv->rst); > + if (ret) { > + clk_disable_unprepare(priv->clk); > + return dev_err_probe(priv->dev, ret, > + "Failed to deassert reset control\n"); > + } > + > + return devm_add_action_or_reset(priv->dev, starfive_peci_clk_reset_rele= ase, > + priv); This could be simplified with devm_clk_get_enabled() and devm_reset_control_get_exclusive_deasserted(). regards Philipp