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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: mathieu.poirier@linaro.org, mike.leach@linaro.org,
	Linu Cherian <lcherian@marvell.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 08/11] coresight: core: Add support for dedicated percpu sinks
Date: Wed, 13 Jan 2021 09:43:47 +0000	[thread overview]
Message-ID: <83939b79-31de-2984-7418-7e4c026dba3a@arm.com> (raw)
In-Reply-To: <1610511498-4058-9-git-send-email-anshuman.khandual@arm.com>

On 1/13/21 4:18 AM, Anshuman Khandual wrote:
> Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> TRBE). To allow quicker access to the sink for a given CPU bound source,
> keep a percpu array of the sink devices. Also, add support for building
> a path to the CPU local sink from the ETM.
> 
> This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> This new sink type is exclusively available and can only work with percpu
> source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
> 
> This defines a percpu structure that accommodates a single coresight_device
> which can be used to store an initialized instance from a sink driver. As
> these sinks are exclusively linked and dependent on corresponding percpu
> sources devices, they should also be the default sink device during a perf
> session.
> 
> Outwards device connections are scanned while establishing paths between a
> source and a sink device. But such connections are not present for certain
> percpu source and sink devices which are exclusively linked and dependent.
> Build the path directly and skip connection scanning for such devices.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>   drivers/hwtracing/coresight/coresight-core.c | 14 ++++++++++++++
>   include/linux/coresight.h                    | 12 ++++++++++++
>   2 files changed, 26 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 0062c89..b300606 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -23,6 +23,7 @@
>   #include "coresight-priv.h"
>   
>   static DEFINE_MUTEX(coresight_mutex);
> +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>   
>   /**
>    * struct coresight_node - elements of a path, from source to sink
> @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
>   	if (csdev == sink)
>   		goto out;
>   
> +	if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> +	    sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> +		_coresight_build_path(sink, sink, path);
> +		found = true;
> +		goto out;
> +	}
> +
>   	/* Not a sink - recursively explore each port found on this element */
>   	for (i = 0; i < csdev->pdata->nr_outport; i++) {
>   		struct coresight_device *child_dev;
> @@ -998,6 +1006,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
>   {
>   	int depth = 0;
>   
> +	if (coresight_is_percpu_source(csdev)) {

On a system without per_cpu sink, this would reset the default sink for the source device
every single time and fallback to searching every single time.
So I think it would be better if did check if the def_sink was not set.
We could fold this into the case below may be. i.e,


	if (!csdev->def_sink) {
		if (coresight_is_percpu_source(csdev))
			csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
		if (!csdev->def_sink)			csdev->def_sink = coresight_find_sink(csdev, &depth);
	}

Otherwise looks good to me.

Suzuki

  reply	other threads:[~2021-01-13  9:45 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-13  4:18 [PATCH V2 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 01/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 02/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 03/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 04/11] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 05/11] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 06/11] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-25 19:22   ` Rob Herring
2021-01-25 22:20     ` Suzuki K Poulose
2021-01-25 23:28       ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 07/11] arm64: Add TRBE definitions Anshuman Khandual
2021-01-13  9:21   ` Suzuki K Poulose
2021-01-15  1:52     ` Anshuman Khandual
2021-02-22 13:55   ` Catalin Marinas
2021-02-22 13:59     ` Catalin Marinas
2021-01-13  4:18 ` [PATCH V2 08/11] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-13  9:43   ` Suzuki K Poulose [this message]
2021-01-15  2:36     ` Anshuman Khandual
2021-01-15 12:31       ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 09/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2021-01-13  9:48   ` Suzuki K Poulose
2021-01-13  4:18 ` [PATCH V2 10/11] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-13 15:28   ` Suzuki K Poulose
2021-01-15  5:29     ` Anshuman Khandual
2021-01-15 12:43       ` Suzuki K Poulose
2021-01-17 12:10         ` Anshuman Khandual
2021-01-13  4:18 ` [PATCH V2 11/11] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-13 15:45   ` Rob Herring
2021-01-14 10:17     ` Suzuki K Poulose
2021-01-14 14:07   ` Rob Herring
2021-01-14 14:47     ` Suzuki K Poulose

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