From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S944695AbdEZT0i convert rfc822-to-8bit (ORCPT ); Fri, 26 May 2017 15:26:38 -0400 Received: from terminus.zytor.com ([65.50.211.136]:48167 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934246AbdEZT0V (ORCPT ); Fri, 26 May 2017 15:26:21 -0400 Date: Fri, 26 May 2017 11:24:39 -0700 User-Agent: K-9 Mail for Android In-Reply-To: References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging To: Linus Torvalds , "Kirill A. Shutemov" CC: "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , Andi Kleen , Dave Hansen , Andy Lutomirski , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List From: hpa@zytor.com Message-ID: <83F4880B-5D1F-4576-A9B6-7DDF4173E2E5@zytor.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On May 26, 2017 8:51:48 AM PDT, Linus Torvalds wrote: >On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov > wrote: >> >> I don't see how kernel threads can use 4-level paging. It doesn't >work >> from virtual memory layout POV. Kernel claims half of full virtual >address >> space for itself -- 256 PGD entries, not one as we would effectively >have >> in case of switching to 4-level paging. For instance, addresses, >where >> vmalloc and vmemmap are mapped, are not canonical with 4-level >paging. > >I would have just assumed we'd map the kernel in the shared part that >fits in the top 47 bits. > >But it sounds like you can't switch back and forth anyway, so I guess >it's moot. > >Where *is* the LA57 documentation, btw? I had an old x86 architecture >manual, so I updated it, but LA57 isn't mentioned in the new one >either. > > Linus As one of the major motivations for LA57 is that we expect that we will have machines with more than 2^46 bytes of memory in the near future, it isn't feasible in most cases to do per-VM LA57. The only case where that even has any utility is for an application to want more than 128 TiB address space on a machine with no more than 64 TiB of RAM. It is kind of a narrow use case, I think. -- Sent from my Android device with K-9 Mail. Please excuse my brevity.