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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from CH8PR12MB9766.namprd12.prod.outlook.com (2603:10b6:610:2b6::10) by IA0PPF864563BFB.namprd12.prod.outlook.com (2603:10b6:20f:fc04::bd7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.10; Fri, 30 Oct 2026 18:28:17 +0000 Received: from CH8PR12MB9766.namprd12.prod.outlook.com ([fe80::be0f:431f:5f27:96d9]) by CH8PR12MB9766.namprd12.prod.outlook.com ([fe80::be0f:431f:5f27:96d9%5]) with mapi id 15.21.0569.009; Fri, 30 Oct 2026 18:28:17 +0000 Message-ID: <83a62ebc-78b6-4442-a097-566b4a2704a9@amd.com> Date: Fri, 30 Oct 2026 13:28:14 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] cxl/port: Unmask AER internal errors for VH endpoints To: Richard Cheng , dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com Cc: iweiny@kernel.org, ming.li@zohomail.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com References: <20261030095951.46080-1-icheng@nvidia.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: <20261030095951.46080-1-icheng@nvidia.com> Content-Type: text/plain; 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Allow cxl_port to use pci_aer_unmask_internal_errors() through > its module-restricted export. > > Verified with QEMU mem-data-ecc injection: the Root Port AER interrupt > fires, the CXL correctable-error trace is emitted, and the endpoint's > CorrIntErr counter increments. > > Signed-off-by: Richard Cheng > --- > drivers/cxl/port.c | 7 +++++++ > drivers/pci/pcie/aer.c | 3 ++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c > index c48216e5078f..c94a310061b0 100644 > --- a/drivers/cxl/port.c > +++ b/drivers/cxl/port.c > @@ -121,6 +121,13 @@ static int cxl_ras_unmask(struct cxl_port *port) > orig_val, val); > } > > + /* > + * RCH errors are reported by the RCEC. VH endpoints report CXL > + * protocol errors as PCIe AER internal errors. > + */ > + if (!is_cxl_restricted(pdev)) > + pci_aer_unmask_internal_errors(pdev); > + > return 0; > } > Hi Richard, The unmasking needs to cover the RCD case as well. The RCD AER is used to mask reporting. The is_cxl_restricted() gate should be removed so the pci_aer_unmask_internal_errors() is called for both the VH and RCD cases. I confirmed Sashiko's finding that the unmasking will never execute, thanks to this early return: if (!dev_is_pci(port->uport_dev)) <<== Fails here return 0; pdev = to_pci_dev(port->uport_dev); For an endpoint port, port->uport_dev is the cxl_memdev, not a PCI device. So dev_is_pci() is false and we return early. The PCI device is `port->uport_dev->parent`. Note, I used base v7.3-rc7. I couldn't find f0c48323b040. - Terry > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index db4f607f889c..94eca22422b7 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -1287,7 +1287,8 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) > * Internal errors are too device-specific to enable generally, however for CXL > * their behavior is standardized for conveying CXL protocol errors. > */ > -EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); > +EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, > + "cxl_core,cxl_port"); > > #ifdef CONFIG_CXL_RAS > bool is_aer_internal_error(struct aer_err_info *info) > > base-commit: f0c48323b0402349530abc60ea908b5f5f40c395