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Wed, 20 May 2026 01:40:02 -0700 (PDT) X-Received: by 2002:a05:6a21:6d9e:b0:39f:2b9e:e489 with SMTP id adf61e73a8af0-3b22e70d3a6mr25668409637.13.1779266402224; Wed, 20 May 2026 01:40:02 -0700 (PDT) Received: from [172.20.10.3] ([27.60.134.77]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c82bb08cde6sm18588546a12.13.2026.05.20.01.39.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 May 2026 01:40:01 -0700 (PDT) Message-ID: <83ff0d14-1cad-4ca5-a512-05773c36cd8d@oss.qualcomm.com> Date: Wed, 20 May 2026 14:09:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 15/16] drm/msm/a6xx: Append SEL regs to dyn pwrup reglist To: Rob Clark , dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Anna Maniscalco , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , open list References: <20260518190735.16236-1-robin.clark@oss.qualcomm.com> <20260518190735.16236-16-robin.clark@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260518190735.16236-16-robin.clark@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=WaY8rUhX c=1 sm=1 tr=0 ts=6a0d7363 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Q/5yxSSCruZ1lXPW2Frkag==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=r2EW3oPWh8cgNxWArIsA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: SSZrC9yPhgSOEZs37YAf0dkW6cqRRnRZ X-Proofpoint-ORIG-GUID: SSZrC9yPhgSOEZs37YAf0dkW6cqRRnRZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDA4MiBTYWx0ZWRfX0KOUwWHbeQZu tOqXYlqPczoB7J6nf8rhvex+VGTGogLqh71YUsWrPPoed3Gje+lpc64KVvenudptw0P9zpuBsNI aFSF4rgPFLPklbn0SShaYXO/tS6ZoOKStem99Y+R8qRn1sDFlxowRSdZbR+9zejir86wWSC2dmc U+SlRiwNbgSCepWH+Ud2W6rTA3eNkhR0eo6OJPO6kBK9OIPXeKDG2zcxfvK538CEegZZdXAQYti yNcgeyquNxa8oyrUuiHxDwiJFJPENVpXzxZ6WHzcLA7HcpVtZuID8khflrU5K341ecOV7lVr2TB F43m8c8u684bXhA8zh1eBDrav2aXSAGlwzwiNBI1YP5Y2W+a3ckOyNs/vIvdXhnWOPMlJWQtTHW GLyTTZ22qX3tzvsuH4LKm68++pA/5/G0Twrcy8B2/Jmr4ziYGyMZX4162sFoZjoyvMZtf5UD3s/ MDgHh+k+/l+pOZxEmSA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200082 On 5/19/2026 12:36 AM, Rob Clark wrote: > This is needed so that SEL reg values are restored on exit from IFPC. > > Signed-off-by: Rob Clark > Reviewed-by: Anna Maniscalco > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +++++++++++++++++++++++++-- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 11 +++- > drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 1 + > 3 files changed, 87 insertions(+), 7 deletions(-) > << snip >> > static void > a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > const struct msm_perfcntr_stream *stream) > { > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > enum adreno_pipe pipe = PIPE_NONE; > + uint32_t *reglist = NULL; > + uint32_t *reglist_sel_start; > + > + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { > + WARN_ON(!a6xx_gpu->pwrup_reglist_emitted); > + > + struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; > + int off = (2 * lock->ifpc_list_len) + > + (2 * lock->preemption_list_len) + > + (3 * a6xx_gpu->dynamic_sel_reglist_offset); > + > + reglist = (uint32_t *)&lock->regs[0]; > + reglist += off; > + reglist_sel_start = reglist; > + > + /* Clear any previously configured SEL reg entries: */ > + lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset; > + > + /* > + * Ensure CP sees the dynamic_list_len update before we > + * start modifying the SEL entries: > + */ > + wmb(); dma_wmb() is a lighter barrier and provides the same ordering for memory writes visible to devices. > + } > > for (unsigned i = 0; i < stream->nr_groups; i++) { > unsigned group_idx = msm_perfcntr_group_idx(stream, i); > @@ -2567,17 +2617,15 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > > const struct msm_perfcntr_counter *counter = &group->counters[base]; > unsigned nr = group_state->allocated_counters; > - OUT_PKT4(ring, counter->select_reg, nr); > - for (unsigned c = 0; c < nr; c++) > - OUT_RING(ring, group_state->countables[c]); > + perfcntr_select(ring, pipe, counter->select_reg, > + group_state->countables, nr, ®list); > > for (unsigned s = 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { > if (!counter->slice_select_regs[s]) > break; > > - OUT_PKT4(ring, counter->slice_select_regs[s], nr); > - for (unsigned c = 0; c < nr; c++) > - OUT_RING(ring, group_state->countables[c]); > + perfcntr_select(ring, pipe, counter->slice_select_regs[s], > + group_state->countables, nr, ®list); > } > } > > @@ -2591,6 +2639,28 @@ a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); > OUT_RING(ring, stream->sel_fence); > > + /* > + * Update the pwrup reglist size before flushing. Kgsl does a shared- > + * memory spinlock dance with SQE to avoid racing with IFPC exit. But > + * we can skip that since the ringbuffer programming will be executed > + * by SQE after dynamic reglist size is updated. So even if we lose > + * the race, the register programming in the rb will overwrite/correct > + * the SEL regs restored by SQE on IFPC exit, before sampling begins. > + */ > + if (reglist) { > + struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; > + unsigned nr_regs = (reglist - reglist_sel_start) / 3; > + > + /* > + * Ensure CP sees updates to the pwrup_reglist before it > + * sees the new (increased) length: > + */ > + wmb(); Same as above. -Akhil