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Date: Wed, 4 Mar 2009 16:32:22 +0200
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Subject: Re: [patch] xtensa: enforce slab alignment to maximum register width
From: Pekka Enberg <penberg@cs.helsinki.fi>
To: Johannes Weiner <jw@emlix.com>
Cc: Chris Zankel <chris@zankel.net>, linux-kernel@vger.kernel.org
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On Wed, Mar 4, 2009 at 3:56 PM, Johannes Weiner <jw@emlix.com> wrote:
> From: Oskar Schirmer <os@emlix.com>
>
> XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
> aligned to this.
>
> Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
> (wordsize) for now.  But the S6000 variant will raise this to 16.
>
> Signed-off-by: Oskar Schirmer <os@emlix.com>
> Signed-off-by: Johannes Weiner <jw@emlix.com>
> ---
>  arch/xtensa/include/asm/processor.h |    2 ++
>  1 file changed, 2 insertions(+)
>
> --- a/arch/xtensa/include/asm/processor.h
> +++ b/arch/xtensa/include/asm/processor.h
> @@ -25,6 +25,8 @@
>  # error Linux requires the Xtensa Windowed Registers Option.
>  #endif
>
> +#define ARCH_SLAB_MINALIGN     XCHAL_DATA_WIDTH
> +

Looks good to me!

Acked-by: Pekka Enberg <penberg@cs.helsinki.fi>