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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id i26-20020a056512007a00b004f4cabba7efsm1895400lfo.198.2023.05.29.01.55.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 May 2023 01:55:53 -0700 (PDT) Message-ID: <8420862d-c292-99aa-3d48-7734a772dab6@linaro.org> Date: Mon, 29 May 2023 11:55:53 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 3/3] clk: qcom: cbf-msm8996: Add support for MSM8996 Pro Content-Language: en-GB To: Konrad Dybcio , Yassine Oudjana , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230527093934.101335-1-y.oudjana@protonmail.com> <20230527093934.101335-4-y.oudjana@protonmail.com> <2d044f14-65c0-be3f-595f-4ddb46df6fef@linaro.org> From: Dmitry Baryshkov In-Reply-To: <2d044f14-65c0-be3f-595f-4ddb46df6fef@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/05/2023 11:18, Konrad Dybcio wrote: > > > On 27.05.2023 11:39, Yassine Oudjana wrote: >> From: Yassine Oudjana >> >> The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the >> difference accordingly. >> >> Signed-off-by: Yassine Oudjana >> --- >> drivers/clk/qcom/clk-cbf-8996.c | 10 ++++++++-- >> 1 file changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c >> index cfd567636f4e..ab988e6f1976 100644 >> --- a/drivers/clk/qcom/clk-cbf-8996.c >> +++ b/drivers/clk/qcom/clk-cbf-8996.c >> @@ -48,7 +48,7 @@ static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = { >> [PLL_OFF_STATUS] = 0x28, >> }; >> >> -static const struct alpha_pll_config cbfpll_config = { >> +static struct alpha_pll_config cbfpll_config = { >> .l = 72, >> .config_ctl_val = 0x200d4828, >> .config_ctl_hi_val = 0x006, >> @@ -137,7 +137,7 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw, >> { >> struct clk_hw *parent; >> >> - if (req->rate < (DIV_THRESHOLD / 2)) >> + if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div)) >> return -EINVAL; >> >> if (req->rate < DIV_THRESHOLD) >> @@ -265,6 +265,11 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) >> /* Switch CBF to use the primary PLL */ >> regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); >> >> + if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) { > If this was a driver for more than 1.5 SoCs, I'd propose using a > different mechanism here (match data flags or something), but since > there aren't (and hopefully won't ever be) more 8996s (automotive etc. > inherit one of these configurations so that doesn't count), I'm willing > to say Fingers crossed for no additional 8996 variants. Reviewed-by: Dmitry Baryshkov > Reviewed-by: Konrad Dybcio -- With best wishes Dmitry