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Mon, 18 Aug 2025 06:48:56 -0700 (PDT) Message-ID: <84498b4b-9023-4a39-bc75-d2b7a495821f@linaro.org> Date: Mon, 18 Aug 2025 14:48:54 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/13] spi: spi-fsl-lpspi: Enumerate all pin configuration definitions To: Frank Li Cc: Mark Brown , Clark Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Larisa Grigore , Larisa Grigore , Ghennadi Procopciuc , Ciprianmarian Costea , s32@nxp.com, linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20250814-james-nxp-lpspi-v1-0-9586d7815d14@linaro.org> <20250814-james-nxp-lpspi-v1-5-9586d7815d14@linaro.org> Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/08/2025 7:10 pm, Frank Li wrote: > On Thu, Aug 14, 2025 at 05:06:45PM +0100, James Clark wrote: >> Add all the possible options, use names more similar to the reference > > Add all the possible pincfg options, > >> manual and convert _OFFSET to _MASK so we can use FIELD_PREP() and >> FIELD_FITS() macros etc. >> >> This will make it slightly easier to add a DT property for this in the >> next commit. > > Make it slightly easier to add a DT property ... > > No funtionality change. > Ack >> >> Signed-off-by: James Clark >> --- >> drivers/spi/spi-fsl-lpspi.c | 21 +++++++++++++++------ >> 1 file changed, 15 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c >> index 79b170426bee..816e48bbc810 100644 >> --- a/drivers/spi/spi-fsl-lpspi.c >> +++ b/drivers/spi/spi-fsl-lpspi.c >> @@ -69,7 +69,11 @@ >> #define DER_RDDE BIT(1) >> #define DER_TDDE BIT(0) >> #define CFGR1_PCSCFG BIT(27) >> -#define CFGR1_PINCFG (BIT(24)|BIT(25)) >> +#define CFGR1_PINCFG_MASK GENMASK(25, 24) >> +#define CFGR1_PINCFG_SIN_IN_SOUT_OUT 0 >> +#define CFGR1_PINCFG_SIN_ONLY 1 >> +#define CFGR1_PINCFG_SOUT_ONLY 2 >> +#define CFGR1_PINCFG_SOUT_IN_SIN_OUT 3 >> #define CFGR1_PCSPOL_MASK GENMASK(11, 8) >> #define CFGR1_NOSTALL BIT(3) >> #define CFGR1_HOST BIT(0) >> @@ -411,8 +415,9 @@ static int fsl_lpspi_dma_configure(struct spi_controller *controller) >> >> static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) >> { >> - u32 temp; >> + u32 temp = 0; >> int ret; >> + u8 pincfg; >> >> if (!fsl_lpspi->is_target) { >> ret = fsl_lpspi_set_bitrate(fsl_lpspi); >> @@ -422,10 +427,14 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) >> >> fsl_lpspi_set_watermark(fsl_lpspi); >> >> - if (!fsl_lpspi->is_target) >> - temp = CFGR1_HOST; >> - else >> - temp = CFGR1_PINCFG; >> + if (!fsl_lpspi->is_target) { >> + temp |= CFGR1_HOST; >> + pincfg = CFGR1_PINCFG_SIN_IN_SOUT_OUT; >> + } else { >> + pincfg = CFGR1_PINCFG_SOUT_IN_SIN_OUT; >> + } >> + temp |= FIELD_PREP(CFGR1_PINCFG_MASK, pincfg); >> + >> if (fsl_lpspi->config.mode & SPI_CS_HIGH) >> temp |= FIELD_PREP(CFGR1_PCSPOL_MASK, >> BIT(fsl_lpspi->config.chip_select)); >> >> -- >> 2.34.1 >>