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Mon, 2 Mar 2026 08:08:44 -0600 Received: from [10.249.132.17] ([10.249.132.17]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 622E8eHX403914; Mon, 2 Mar 2026 08:08:41 -0600 Message-ID: <845474f9-a809-4b6f-b10f-2d79284b0a60@ti.com> Date: Mon, 2 Mar 2026 19:38:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 1/3] crypto: ti - Add support for AES-CTR in DTHEv2 driver To: Herbert Xu CC: "David S. Miller" , Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , "Vishal Mahaveer" , Praneeth Bajjuri , , References: <20260120144408.606911-1-t-pratham@ti.com> <20260120144408.606911-2-t-pratham@ti.com> Content-Language: en-US From: T Pratham In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|DS4PPF376CF97B3:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c2fcba5-8066-4a80-e7d3-08de7865379a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|34020700016|376014; X-Microsoft-Antispam-Message-Info: in/KGvJy5JC1bACdvY5+GZU6UI3wcE0zXolBpm8fG2V2SjZtHEOOTG1+JbCpCg6ya7RWk2IisGLwj7TaX0b74l3t3dMGBTBbDAelBsCLHKXhStw7BKbwxuctMby4C585zYjBaScsfrsOJgzBfyCFu1bjOS54F5PzFfk8dCeO1R2MK9eZSjkbTh4835jYLNyVtpIHDMZZWSoie7ruypt1B2AUU+ccF22aAiM1UBeXLxyZa129bw6AkOyNVKzX6gpDOcDphEh6KH7jBqPOCvaO81iRcUNhTgkRqki3l3+MvWelBlCbu0fp3xbm7E3uQFiPYwiUctlu3k3YRorj3o5ywi6pBIoHz6vtSRPJyHspy+zyWHM37VRTXEC5yKAdPnAZ+SV9LUfJWk4i6987pbxSJFhYObaZzugXH3MyLhsS6Bkm8DXZt3YpQm/1K1Cfzbkl7np1IntJEmVsY7rPuKmwf+vlukK03hN/iHfhsoBePuASetLW6oJiexz/P/xYd//XHIVGpTupTVFQMUMezZ61m4vk0+OIKLHjwf8MlPRADmO7XehTWMbBRwdYAJDOBV4ej8nGf+alJfQcFOepPM0p2tCdiAgECjgLB0ctkHQGyTOrWScssGl26NA6dirprFAzUr5iKSLa9+Mcg3n1K7gAQ/zscRSOn5aLyBtQuHZ2lBvfxHIl7YcfH+mV1dzh4fdRFqnpSk3cIRoSuKM7CtR+jhXuWrGv6SLVAQQgzJolmM1Zh4shzC2CJuxrD6zrPfOIcTM16Hwo8gLzVN6THB06JYUCVcq+i5MLSkb3OhhTG4L07JtLxmOHP43c0iLYHFwDSosmQewCzUHRmgU0Jhiopw== X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(34020700016)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SBE4+7Wk9GXVj6AQFJyarJd19MXqcXXg/hizyn4dy/0pTwT2Bi2uWcBqp3KHF/4FOLaYG2a3YgVd53/HmchRsf21F7ummpFZ6MwXbCaTiiguKxybBjWK6WSVjCR06TdBPyvjyv1OF6su59Rznsxr+OKVnsSsbodL34hP8dp0RRXLE1XN3m9OY01dD06C8tHIm6BDR7tN05eI4fwHZpUeofLHIEhBMPhHrJTxCNC8pEPlbQSkacrJneZItJcmU94r9UuW4bvi+mboUVpVqtokAVxQ33rPdC75nWVlT2laZ9x5lEUTGOKrs861MpiT7tltYroEWUpqaxSqLpCdMCM6NIe7ayKzZgUsZtv3HqHpwhY9gLMZS1K0Rg4kj51AAF3Y7qsSBxxTJ9qCplpE2Fquu2O7wMs35l6F8LTGstonwce+3/IBbKTkudiYohiqiJwD X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2026 14:08:45.1877 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c2fcba5-8066-4a80-e7d3-08de7865379a X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PPF376CF97B3 On 28-02-2026 14:10, Herbert Xu wrote: > On Fri, Feb 06, 2026 at 05:07:13PM +0530, T Pratham wrote: >> >> The DMA (at least UDMA in K3 SoCs) sends/receives all the mapped length. >> If I have the dst sg mapped with length (len + x) but write len in >> crypto hardware, the DMA gets stuck waiting for hardware to send the >> extra x len. Similar issue in reverse as well. >> >> Also, FWIW, I'm restoring the len in SG list correctly at the end. > > If that's the case wouldn't it also break if the caller supplied > an SG list that's longer than req->cryptlen? There is no requirement > that the SG list must be exactly as long as req->cryptlen and it > can contain extra data at the end. > > Perhaps you should use sg_split like sa2ul. > > Thanks, Understood. Will update accordingly. Also, sent an updated series twice with other changes. Here, for reference, is the latest one: https://lore.kernel.org/all/20260226125441.3559664-1-t-pratham@ti.com/ -- Regards T Pratham