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Wed, 09 Apr 2025 16:10:30 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 539GAUM3019518 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Apr 2025 16:10:30 GMT Received: from [10.216.18.165] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Apr 2025 09:10:26 -0700 Message-ID: <847cdac2-e048-ea76-3e59-6121b6c5dc5e@quicinc.com> Date: Wed, 9 Apr 2025 21:40:23 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 2/6] media: platform: qcom/iris: add power_off_controller to vpu_ops Content-Language: en-US To: Neil Armstrong , Dikshita Agarwal , Abhinav Kumar , "Mauro Carvalho Chehab" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel CC: , , , , "Bryan O'Donoghue" References: <20250409-topic-sm8x50-iris-v10-v4-0-40e411594285@linaro.org> <20250409-topic-sm8x50-iris-v10-v4-2-40e411594285@linaro.org> From: Vikash Garodia In-Reply-To: <20250409-topic-sm8x50-iris-v10-v4-2-40e411594285@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: etj7PzCQQONbhrv23B5fKO0qTLdAiS6Z X-Authority-Analysis: v=2.4 cv=T7OMT+KQ c=1 sm=1 tr=0 ts=67f69bf6 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=KLkN61wKYaU8GyH-Q9sA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: etj7PzCQQONbhrv23B5fKO0qTLdAiS6Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_05,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 mlxscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504090103 On 4/9/2025 8:08 PM, Neil Armstrong wrote: > In order to support the SM8650 iris33 hardware, we need to provide a > specific constoller power off sequences via the vpu_ops callbacks. > > Add the callback, and use the current helper for currently supported > platforms. > > Reviewed-by: Bryan O'Donoghue > Reviewed-by: Dikshita Agarwal > Tested-by: Bryan O'Donoghue # x1e Dell > Signed-off-by: Neil Armstrong > --- > drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + > drivers/media/platform/qcom/iris/iris_vpu3.c | 1 + > drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- > drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ > 4 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c > index 8f502aed43ce2fa6a272a2ce14ff1ca54d3e63a2..7cf1bfc352d34b897451061b5c14fbe90276433d 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu2.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c > @@ -34,5 +34,6 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) > > const struct vpu_ops iris_vpu2_ops = { > .power_off_hw = iris_vpu_power_off_hw, > + .power_off_controller = iris_vpu_power_off_controller, > .calc_freq = iris_vpu2_calc_freq, > }; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/platform/qcom/iris/iris_vpu3.c > index b484638e6105a69319232f667ee7ae95e3853698..13dab61427b8bd0491b69a9bc5f5144d27d17362 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3.c > @@ -118,5 +118,6 @@ static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t data_siz > > const struct vpu_ops iris_vpu3_ops = { > .power_off_hw = iris_vpu3_power_off_hardware, > + .power_off_controller = iris_vpu_power_off_controller, > .calc_freq = iris_vpu3_calculate_frequency, > }; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c > index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..268e45acaa7c0e3fe237123c62f0133d9dface14 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c > @@ -211,7 +211,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) > return -EAGAIN; > } > > -static int iris_vpu_power_off_controller(struct iris_core *core) > +int iris_vpu_power_off_controller(struct iris_core *core) > { > u32 val = 0; > int ret; > @@ -264,7 +264,7 @@ void iris_vpu_power_off(struct iris_core *core) > { > dev_pm_opp_set_rate(core->dev, 0); > core->iris_platform_data->vpu_ops->power_off_hw(core); > - iris_vpu_power_off_controller(core); > + core->iris_platform_data->vpu_ops->power_off_controller(core); > iris_unset_icc_bw(core); > > if (!iris_vpu_watchdog(core, core->intr_status)) > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h > index 63fa1fa5a4989e48aebdb6c7619c140000c0b44c..f8965661c602f990d5a7057565f79df4112d097e 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h > @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; > > struct vpu_ops { > void (*power_off_hw)(struct iris_core *core); > + int (*power_off_controller)(struct iris_core *core); > u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); > }; > > @@ -22,6 +23,7 @@ void iris_vpu_clear_interrupt(struct iris_core *core); > int iris_vpu_watchdog(struct iris_core *core, u32 intr_status); > int iris_vpu_prepare_pc(struct iris_core *core); > int iris_vpu_power_on(struct iris_core *core); > +int iris_vpu_power_off_controller(struct iris_core *core); > void iris_vpu_power_off_hw(struct iris_core *core); > void iris_vpu_power_off(struct iris_core *core); Reviewed-by: Vikash Garodia