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[98.61.227.136]) by smtp.gmail.com with ESMTPSA id 25-20020a5ea519000000b007b42bf452f4sm462064iog.33.2024.01.05.07.42.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Jan 2024 07:42:34 -0800 (PST) Message-ID: <84a06035-ed88-408e-9441-d36de9fbd5ad@linaro.org> Date: Fri, 5 Jan 2024 09:42:32 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/5] support ipq5332 platform Content-Language: en-US To: Andrew Lunn , Sergey Ryazanov Cc: Jie Luo , agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, hkallweit1@gmail.com, linux@armlinux.org.uk, robert.marko@sartura.hr, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com References: <20231225084424.30986-1-quic_luoj@quicinc.com> <8ef607b9-1fc6-485b-a6fb-a8d468cc1954@lunn.ch> From: Alex Elder In-Reply-To: <8ef607b9-1fc6-485b-a6fb-a8d468cc1954@lunn.ch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/5/24 7:52 AM, Andrew Lunn wrote: > On Fri, Jan 05, 2024 at 04:48:31AM +0200, Sergey Ryazanov wrote: >> Hi Luo, >> >> thank you for explaining the case in such details. I also have checked the >> related DTSs in the Linaro repository to be more familiar with the I/O mem >> layout. Specifically I checked these two, hope they are relevant to the >> discussion: >> https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r3/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r3/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> >> Please find my comments below. > > Hi Sergey > > There is a second thread going on, focused around the quad PHY. See: > > https://lore.kernel.org/netdev/60b9081c-76fa-4122-b7ae-5c3dcf7229f9@lunn.ch/ > > Since it is very hard to get consistent information out of Luo, he has > annoyed nearly all the PHY maintainers and all the DT maintainers, i'm > going back to baby steps, focusing on just the quad pure PHY, and > trying to get that understood and correctly described in DT. > > However, does Linaro have any interest in just taking over this work, > or mentoring Luo? I will reach out to Qualcomm to discuss options here. We can certainly offer to mentor, and I think we might even be able to take over the work. But I won't be able to get any resolution on this until next week. Jie Luo, please hold off on further posts on this for a little while. I will report back once I've been able to discuss this with folks at Qualcomm. -Alex > > Andrew >