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Fri, 17 Jul 2026 11:23:23 -0700 (PDT) Message-ID: <84a2bc54-3f2c-403f-92c5-d7cdc15d4072@sifive.com> Date: Fri, 17 Jul 2026 13:23:21 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] riscv: mm: Apply Svinval in update_mmu_cache() To: Xu Lu , paul.walmsley@sifive.com, klarasmodin@gmail.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com References: <20260715132009.10634-1-luxu.kernel@bytedance.com> <20260715132009.10634-3-luxu.kernel@bytedance.com> Content-Language: en-US From: Samuel Holland In-Reply-To: <20260715132009.10634-3-luxu.kernel@bytedance.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Xu Lu, On 2026-07-15 8:20 AM, Xu Lu wrote: > Use Svinval in update_mmu_cache_range() when the extension is available. > > Signed-off-by: Xu Lu > --- > arch/riscv/include/asm/pgtable.h | 8 ++++++++ > arch/riscv/include/asm/tlbflush.h | 18 ++++++++++++++++++ > arch/riscv/mm/tlbflush.c | 18 ------------------ > 3 files changed, 26 insertions(+), 18 deletions(-) > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index 9926556099ae..823805cc465a 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -578,6 +578,14 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, > if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) > return; > > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) { > + local_sfence_w_inval(); > + while (nr--) > + local_sinval_vma(address + nr * PAGE_SIZE, asid); > + local_sfence_inval_ir(); > + return; > + } > + This duplicates the logic in local_flush_tlb_range_threshold_asid(). If you exported local_flush_tlb_range_mm(), you could use that here without rearranging any of the other functions, and it also be able to reuse the threshold logic, which is important on platforms that set local_flush_tlb_range_mm = 1 to always do full-address-space flushes. Regards, Samuel > /* > * The kernel assumes that TLBs don't cache invalid entries, but > * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > index 7c2cd5cc92d3..9636d07fe9ee 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -20,6 +20,24 @@ static inline unsigned long get_mm_asid(struct mm_struct *mm) > return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID; > } > > +static inline void local_sfence_inval_ir(void) > +{ > + asm volatile(SFENCE_INVAL_IR() ::: "memory"); > +} > + > +static inline void local_sfence_w_inval(void) > +{ > + asm volatile(SFENCE_W_INVAL() ::: "memory"); > +} > + > +static inline void local_sinval_vma(unsigned long vma, unsigned long asid) > +{ > + if (asid != FLUSH_TLB_NO_ASID) > + asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); > + else > + asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); > +} > + > static inline void local_flush_tlb_all(void) > { > __asm__ __volatile__ ("sfence.vma" : : : "memory"); > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 73c226f719c7..962db300a166 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -11,24 +11,6 @@ > > #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) > > -static inline void local_sfence_inval_ir(void) > -{ > - asm volatile(SFENCE_INVAL_IR() ::: "memory"); > -} > - > -static inline void local_sfence_w_inval(void) > -{ > - asm volatile(SFENCE_W_INVAL() ::: "memory"); > -} > - > -static inline void local_sinval_vma(unsigned long vma, unsigned long asid) > -{ > - if (asid != FLUSH_TLB_NO_ASID) > - asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); > - else > - asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); > -} > - > /* > * Flush entire TLB if number of entries to be flushed is greater > * than the threshold below.