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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE3MDI3NyBTYWx0ZWRfX07/CCUykmJUB 8JxLAZmhFGs2HRARDykVT+MUZbfjPrc1TmZiMcF0zadcJlVbhTIacdVQvuv16lXUFcrQ+xcAsCD Lq9HF+WfDoFh5M4NH+f1zEg02yQrUjM= X-Authority-Analysis: v=2.4 cv=XttvqlF9 c=1 sm=1 tr=0 ts=6aac3da4 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=/ba+GChBmZZUisokHISCpA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=pOrFmiSUyACN_rSOyqsA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: J06zY2B9hjUxWfa4mzPQeTcHcXWCs3ux X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE3MDI3NyBTYWx0ZWRfXyFf+43v/mjYz isQw3YAXMpHWBRVjdJEWRMyiGYDX/fbsFZmSoXr6sjsZUqG1zfyuYnQsrp6Gnm0m6i8pqwxgcvA wnl0gGVi60IDKMV7GN1gbV/yvnw1QZ/boV7Ar2e0WgPmPcpMTxXl//UdkbciPRUE9ZmSGO5NcBo gDxEZUfC5bM6qHNssDmGyE1R0s5bbiAGJttijCzv/aWMB2jV+uMccD406pCjxoof+EkVLBkBK6a At5cIQUwFAy1uPMr/fnLA/OSs2urlPNa8res5uzevF9N1BjgaMySKdZt/96oexspTHcTY6zTKKH HTj6oyAS6U/vtHOXzBNFw5cSt+M2Qy+GdAdA1g+p/QQZr42daViUm8Wuryma/shkA2DGACorpJL VqZxV5jpLqvrnYka9dpxM2bcj/RCMSXjUOxleQd6U5SID/SMlAqpDQDToKFG94BHJ4XG9YWk+A5 hGKlED6JSd0+ySczYUA== X-Proofpoint-GUID: J06zY2B9hjUxWfa4mzPQeTcHcXWCs3ux X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_04,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609170277 On 9/12/2026 6:34 PM, Jyothi Kumar Seerapu wrote: > Add support in the Qualcomm GPI (Generic Packet Interface) DMA engine > for I2C High-Speed (HS) mode transfers > > Introduce support for CONFIG1 Transfer Ring Element (TRE) to convey > HS-specific timing parameters to the Qualcomm GPI DMA engine. > > Define a new gpi_i2c_config1 structure containing tcycle_cnt and > tlow_cnt fields, with default values of 28 and 38 respectively, > as required for 3.4 MHz HS mode operation. > > Signed-off-by: Jyothi Kumar Seerapu > --- > drivers/dma/qcom/gpi.c | 56 +++++++++++++++++++++++++++++++++++----- > include/linux/dma/qcom-gpi-dma.h | 28 +++++++++++++++++++- > 2 files changed, 76 insertions(+), 8 deletions(-) [...] > struct gpi_desc { > struct virt_dma_desc vd; > @@ -1631,7 +1637,7 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, > struct gpi_tre *tre; > unsigned int i; > > - /* first create config tre if applicable */ > + /* first create config0 tre if applicable */ But the variable name is still set_config, not set_config0 ?> if (i2c->set_config) { > tre = &desc->tre[tre_idx]; > tre_idx++; > @@ -1645,20 +1651,48 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, > tre->dword[1] = 0; > > tre->dword[2] = u32_encode_bits(i2c->clk_div, TRE_C0_CLK_DIV); > + tre->dword[2] |= u32_encode_bits(i2c->clk_src, TRE_C0_CLK_SRC); > > tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE); > tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); > } > > - /* create the GO tre for Tx */ > - if (i2c->op == I2C_WRITE) { > + /* Create CONFIG1 TRE if requested */ same style as set_config, write in lower case.> + if (i2c->set_config1) { > tre = &desc->tre[tre_idx]; > tre_idx++; > > + /* CONFIG1 TRE with timing parameters */ Lower or upper letters ?> + tre->dword[0] = u32_encode_bits(i2c->config1.tlow_cnt, TRE_I2C_C1_TLOW); > + tre->dword[0] |= u32_encode_bits(i2c->config1.tcycle_cnt, TRE_I2C_C1_TCYCLE); > + tre->dword[1] = 0; > + tre->dword[2] = 0; > + tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG1, TRE_FLAGS_TYPE); > + tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); > + } > + > + /* create the GO tre for Tx */ tre/TRE ? keep it uniform way across.> + if (i2c->op == I2C_WRITE || i2c->op == I2C_HS_WRITE) { > + u8 master_code = 0; > + u32 cmd_opcode; > + bool is_hs_mode = false; > + > + tre = &desc->tre[tre_idx]; > + tre_idx++; > + > + is_hs_mode = (i2c->op == I2C_HS_WRITE || i2c->op == I2C_HS_READ); > + > + /* Select HS-mode or standard I2C opcode */ Should you move this inside and just above selection cmd_opcode ? I think the comment is covering multi_msg condition.> if (i2c->multi_msg) > - tre->dword[0] = u32_encode_bits(I2C_READ, TRE_I2C_GO_CMD); > + cmd_opcode = is_hs_mode ? I2C_HS_READ : I2C_READ; > else > - tre->dword[0] = u32_encode_bits(i2c->op, TRE_I2C_GO_CMD); > + /* I2C HS write vs Regular I2C write */ > + cmd_opcode = is_hs_mode ? I2C_HS_WRITE : i2c->op; > + > + tre->dword[0] = u32_encode_bits(cmd_opcode, TRE_I2C_GO_CMD); > + > + if (is_hs_mode) > + tre->dword[0] |= u32_encode_bits(master_code, TRE_I2C_GO_MASTER_CODE); > > tre->dword[0] |= u32_encode_bits(i2c->addr, TRE_I2C_GO_ADDR); > tre->dword[0] |= u32_encode_bits(i2c->stretch, TRE_I2C_GO_STRETCH); > @@ -1674,7 +1708,7 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, > tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); > } [...] > /** > @@ -62,15 +82,19 @@ enum i2c_op { > * @high_count: high period of clock > * @low_count: low period of clock > * @clk_div: source clock divider > + * @clk_src: source clock > * @addr: i2c bus address > * @stretch: stretch the clock at eot > - * @set_config: set peripheral config > + * @set_config: set peripheral config (CONFIG0) set_config0 now ?> + * @set_config1: set peripheral config1 (CONFIG1) purpose or usage not clear, looks mostly similar to variable name.> + * @config1: I2C HS mode timing configuration (CONFIG1 TRE parameters) > * @rx_len: receive length for buffer > * @op: i2c cmd > * @multi_msg: is part of multi i2c r-w msgs > */ > struct gpi_i2c_config { > u8 set_config; > + u8 set_config1; > u8 pack_enable; > u8 cycle_count; > u8 high_count; > @@ -78,6 +102,8 @@ struct gpi_i2c_config { > u8 addr; > u8 stretch; > u16 clk_div; > + u32 clk_src; > + struct gpi_i2c_config1 config1; > u32 rx_len; > enum i2c_op op; > bool multi_msg; >