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Wed, 20 Jul 2022 19:02:56 -0700 (PDT) Received: from [192.168.255.10] ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id z14-20020a62d10e000000b005289753448fsm306997pfg.123.2022.07.20.19.02.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Jul 2022 19:02:56 -0700 (PDT) Message-ID: <84e1a911-d4f9-8984-a548-62100aafd035@gmail.com> Date: Thu, 21 Jul 2022 10:02:49 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 3/7] KVM: x86/pmu: Avoid setting BIT_ULL(-1) to pmu->host_cross_mapped_mask Content-Language: en-US To: Sean Christopherson Cc: Paolo Bonzini , Jim Mattson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu References: <20220713122507.29236-1-likexu@tencent.com> <20220713122507.29236-4-likexu@tencent.com> From: Like Xu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/7/2022 8:45 am, Sean Christopherson wrote: > On Wed, Jul 13, 2022, Like Xu wrote: >> From: Like Xu >> >> In the extreme case of host counters multiplexing and contention, the >> perf_event requested by the guest's pebs counter is not allocated to any >> actual physical counter, in which case hw.idx is bookkept as -1, >> resulting in an out-of-bounds access to host_cross_mapped_mask. >> >> Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") >> Signed-off-by: Like Xu >> --- >> arch/x86/kvm/vmx/pmu_intel.c | 11 +++++------ >> 1 file changed, 5 insertions(+), 6 deletions(-) >> >> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c >> index 53ccba896e77..1588627974fa 100644 >> --- a/arch/x86/kvm/vmx/pmu_intel.c >> +++ b/arch/x86/kvm/vmx/pmu_intel.c >> @@ -783,20 +783,19 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) >> void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) >> { >> struct kvm_pmc *pmc = NULL; >> - int bit; >> + int bit, hw_idx; >> >> for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl, >> X86_PMC_IDX_MAX) { >> pmc = intel_pmc_idx_to_pmc(pmu, bit); >> >> if (!pmc || !pmc_speculative_in_use(pmc) || >> - !intel_pmc_is_enabled(pmc)) >> + !intel_pmc_is_enabled(pmc) || !pmc->perf_event) >> continue; >> >> - if (pmc->perf_event && pmc->idx != pmc->perf_event->hw.idx) { >> - pmu->host_cross_mapped_mask |= >> - BIT_ULL(pmc->perf_event->hw.idx); >> - } >> + hw_idx = pmc->perf_event->hw.idx; >> + if (hw_idx != pmc->idx && hw_idx != -1) > > How about "hw_idx > 0" so that KVM is a little less dependent on perf's exact > behavior? A comment here would be nice too. The "hw->idx = 0" means that it occupies counter 0, so this part will look like this: hw_idx = pmc->perf_event->hw.idx; /* make it a little less dependent on perf's exact behavior */ if (hw_idx != pmc->idx && hw_idx > -1) pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx); , what do you think ? > >> + pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx); >> } >> } >> >> -- >> 2.37.0 >>