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([2a01:e0a:3d9:2080:94e4:fa88:414d:e1ad]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b53f203afsm37294740f8f.39.2025.11.19.00.22.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Nov 2025 00:22:01 -0800 (PST) Message-ID: <84e53d61-ef32-4f15-aa51-132acb83c52d@linaro.org> Date: Wed, 19 Nov 2025 09:22:00 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v3 2/3] phy: qcom: edp: Make the number of clocks flexible To: Abel Vesa , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Dmitry Baryshkov , Konrad Dybcio , Sibi Sankar , Rajendra Nayak Cc: Johan Hovold , Taniya Das , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20250909-phy-qcom-edp-add-missing-refclk-v3-0-4ec55a0512ab@linaro.org> <20250909-phy-qcom-edp-add-missing-refclk-v3-2-4ec55a0512ab@linaro.org> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250909-phy-qcom-edp-add-missing-refclk-v3-2-4ec55a0512ab@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/9/25 09:33, Abel Vesa wrote: > On X Elite, the DP PHY needs another clock called ref, while all other > platforms do not. > > The current X Elite devices supported upstream work fine without this > clock, because the boot firmware leaves this clock enabled. But we should > not rely on that. Also, even though this change breaks the ABI, it is > needed in order to make the driver disables this clock along with the > other ones, for a proper bring-down of the entire PHY. > > So in order to handle these clocks on different platforms, make the driver > get all the clocks regardless of how many there are provided. > > Cc: stable@vger.kernel.org # v6.10 > Fixes: db83c107dc29 ("phy: qcom: edp: Add v6 specific ops and X1E80100 platform support") > Signed-off-by: Abel Vesa > --- > drivers/phy/qualcomm/phy-qcom-edp.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c > index f1b51018683d51df064f60440864c6031638670c..ca9bb9d70e29e1a132bd499fb9f74b5837acf45b 100644 > --- a/drivers/phy/qualcomm/phy-qcom-edp.c > +++ b/drivers/phy/qualcomm/phy-qcom-edp.c > @@ -103,7 +103,9 @@ struct qcom_edp { > > struct phy_configure_opts_dp dp_opts; > > - struct clk_bulk_data clks[2]; > + struct clk_bulk_data *clks; > + int num_clks; > + > struct regulator_bulk_data supplies[2]; > > bool is_edp; > @@ -218,7 +220,7 @@ static int qcom_edp_phy_init(struct phy *phy) > if (ret) > return ret; > > - ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); > + ret = clk_bulk_prepare_enable(edp->num_clks, edp->clks); > if (ret) > goto out_disable_supplies; > > @@ -885,7 +887,7 @@ static int qcom_edp_phy_exit(struct phy *phy) > { > struct qcom_edp *edp = phy_get_drvdata(phy); > > - clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); > + clk_bulk_disable_unprepare(edp->num_clks, edp->clks); > regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); > > return 0; > @@ -1092,11 +1094,9 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) > if (IS_ERR(edp->pll)) > return PTR_ERR(edp->pll); > > - edp->clks[0].id = "aux"; > - edp->clks[1].id = "cfg_ahb"; > - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); > - if (ret) > - return ret; > + edp->num_clks = devm_clk_bulk_get_all(dev, &edp->clks); > + if (edp->num_clks < 0) > + return dev_err_probe(dev, edp->num_clks, "failed to parse clocks\n"); > > edp->supplies[0].supply = "vdda-phy"; > edp->supplies[1].supply = "vdda-pll"; > Reviewed-by: Neil Armstrong