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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-43d43fdeb79sm225846615e9.25.2025.03.26.01.06.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Mar 2025 01:06:35 -0700 (PDT) Message-ID: <84ed89d5-91af-445b-96e6-2c1e41d65294@linaro.org> Date: Wed, 26 Mar 2025 09:06:34 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] clocksource/drivers/nxp-timer: Add the System Timer Module for the s32g platform To: Ghennadi Procopciuc , tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Thomas Fossati , Larisa Grigore , Ghennadi Procopciuc , Maxime Coquelin , Alexandre Torgue , "moderated list:ARM/STM32 ARCHITECTURE" , "moderated list:ARM/STM32 ARCHITECTURE" , NXP S32 Linux Team References: <20250324100008.346009-1-daniel.lezcano@linaro.org> <20250324100008.346009-2-daniel.lezcano@linaro.org> <8c208e8c-2e1e-430c-916a-dbc6732881b0@linaro.org> <065d6f32-3161-8316-bbbd-4da18eef839b@oss.nxp.com> <098c5de8-9291-4f3e-a276-500825cac7c5@linaro.org> <068713cb-47ca-ae26-e113-9f5026be9196@oss.nxp.com> <50d2c651-746e-4ddd-4036-f72742a622f8@oss.nxp.com> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 26/03/2025 08:44, Ghennadi Procopciuc wrote: > On 3/25/2025 3:54 PM, Daniel Lezcano wrote: >> On 25/03/2025 14:21, Ghennadi Procopciuc wrote: >>> On 3/25/2025 2:51 PM, Daniel Lezcano wrote: [ ... ] >>>>> >>>>> This wouldn't be the case if the STM is kept running/counting during >>>>> the >>>>> clock event setup, with only the clock event interrupt being disabled >>>>> (CCR.CEN). >>>> >>>> Are you asking to use two different channels for the same STM instance, >>>> one for the clocksource and one for the clockevent ? >>>> >>> >>> I suggested using the CNT register to obtain the count for the clock >>> source, while using one of the STM channels for the clock event. >> >> Ah, ok. >> >> I think it is preferable to keep them separated to keep the code >> modular. Given the number of STM on the platform, it does not hurt >> > > The S32G2 and S32G3 are SoCs featuring a diverse set of cores. Linux is > expected to run on Cortex-A53 cores, while other software stacks will > operate on Cortex-M cores. The number of STM instances has been sized to > include at most one instance per core. Allocating six instances (1 clock > source, 1 broadcast clock event, and 4 clock events for all A53 cores) > to Linux on the S32G2 leaves the M7 software stacks without adequate STM > coverage. Mmh, right. From this perspective it makes sense. > Additionally, the proposed implementation uses only one STM channel out > of four, which is not optimal hardware usage. I suggest using all STM > channels instead of limiting it to a single channel per instance, given > that the driver already uses a global structure to pair STM instances > with cores. This approach will optimize the number of instances required > by Linux and leverage the capabilities of each STM. -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog