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Tue, 03 Sep 2024 22:20:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 483MKmIm029647 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Sep 2024 22:20:48 GMT Received: from [10.134.70.212] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 3 Sep 2024 15:20:47 -0700 Message-ID: <85022ded-962a-47ac-a083-88db7cd81f0f@quicinc.com> Date: Tue, 3 Sep 2024 15:20:47 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/21] drm/msm/dpu: add CWB entry to catalog for SM8650 To: Dmitry Baryshkov CC: Rob Clark , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , , , , , , Rob Clark References: <20240829-concurrent-wb-v1-0-502b16ae2ebb@quicinc.com> <20240829-concurrent-wb-v1-8-502b16ae2ebb@quicinc.com> Content-Language: en-US From: Jessica Zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GLe-fU_ol172R9bwXyOeiuZRzFuLLWlG X-Proofpoint-ORIG-GUID: GLe-fU_ol172R9bwXyOeiuZRzFuLLWlG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-03_10,2024-09-03_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2409030179 On 8/30/2024 10:13 AM, Dmitry Baryshkov wrote: > On Thu, Aug 29, 2024 at 01:48:29PM GMT, Jessica Zhang wrote: >> From: Esha Bharadwaj >> >> Add new block for concurrent writeback mux to HW catalog and change >> pingpong index names to distinguish between general use pingpong blocks >> and pingpong blocks dedicated for concurrent writeback > > Please split into two commits. Hi Dmitry, Sounds good > >> >> Signed-off-by: Esha Bharadwaj >> Signed-off-by: Jessica Zhang >> --- >> .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 29 +++++++++++++++++++--- >> .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 +-- >> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 +-- >> .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 +-- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++++++++++ >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 8 +++--- >> 6 files changed, 48 insertions(+), 14 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h >> index eb5dfff2ec4f..ce2773029763 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h >> @@ -252,25 +252,25 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { >> .merge_3d = MERGE_3D_2, >> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), >> }, { >> - .name = "pingpong_6", .id = PINGPONG_6, >> + .name = "pingpong_6", .id = PINGPONG_CWB_0, > > Should we also rename such blocks? Sure, I can change the name to match the id Thanks, Jessica Zhang > >> .base = 0x66000, .len = 0, >> .features = BIT(DPU_PINGPONG_DITHER), >> .sblk = &sc7280_pp_sblk, >> .merge_3d = MERGE_3D_3, > > > -- > With best wishes > Dmitry