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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by MN1PEPF0000F0E4.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Tue, 30 Jun 2026 18:11:49 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Tue, 30 Jun 2026 13:11:44 -0500 Received: from nigeria-2635-os.amd.com (10.180.168.240) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Tue, 30 Jun 2026 11:10:46 -0700 From: Ashish Kalra To: , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v10 2/6] x86/sev: Initialize RMPOPT configuration MSRs Date: Tue, 30 Jun 2026 18:10:13 +0000 Message-ID: <8518e02c46d6edf1f37a180569c708a3cfa7c413.1782841284.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E4:EE_|IA1PR12MB8262:EE_ X-MS-Office365-Filtering-Correlation-Id: 8daa4bec-c030-463e-8769-08ded6d30dff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|7416014|23010399003|1800799024|18002099003|22082099003|11063799006|5023799004|56012099006|6133799003|921020|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PbJdZhxa0y51mqQPR1HvIyzquM33aIGqdOhrSXtIxtxPi8L54DYEo3H3rJZJW7WRRQKXeOTVTo0qf9Wg8++MArKMsOF+4tIVTkvVbzydTa+QqEN1Sd3634WKgHnB58CU+TIL7Ti4VDqGniys/krqSQxK/4USzmQSHJhZiH8f6HkIJGg58MoxAH3TSXrJOZF2BxQ+RIaIht8b1oFiRX2FhRjtTAopDo4ROwSS3K/UQiRnH/WhJlDuT+1hVoMBeev7Z54yD+FrI/P/L0LJ9ofqrWoxL3roBszCK/2jD9di+vtXOWBp4FnvWUKoVX8hm3Z4jfofnV9/CVXBbfnXJ008ZrC0F5iVlYrm3AaqVWOPvsJHxUVuh619we2m2L2bxV+h4yOmzBplmVaUjhWYLZOtuP+pNtAMHIbqW9vUnbsjckfqaueIlWFjEG9Xz3B/fH6T X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2026 18:11:49.4057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8daa4bec-c030-463e-8769-08ded6d30dff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8262 From: Ashish Kalra The new RMPOPT instruction helps manage per-CPU RMP optimization structures inside the CPU. It takes a 1GB-aligned physical address and either returns the status of the optimizations or tries to enable the optimizations. Per-CPU RMPOPT tables support at most 2 TB of addressable memory for RMP optimizations. Initialize the per-CPU RMPOPT table base to the starting physical address. This enables RMP optimization for up to 2 TB of system RAM on all CPUs. Additionally, add support to setup and enable RMPOPT once SNP is enabled and initialized. Suggested-by: Thomas Lendacky Suggested-by: Dave Hansen Reviewed-by: Dave Hansen Signed-off-by: Ashish Kalra --- arch/x86/coco/core.c | 2 + arch/x86/include/asm/msr-index.h | 3 ++ arch/x86/include/asm/sev.h | 4 ++ arch/x86/virt/svm/sev.c | 70 ++++++++++++++++++++++++++++++++ drivers/crypto/ccp/sev-dev.c | 3 ++ 5 files changed, 82 insertions(+) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index 989ca9f72ba3..f0ed6c62d86c 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -16,6 +16,7 @@ #include #include #include +#include enum cc_vendor cc_vendor __ro_after_init = CC_VENDOR_NONE; SYM_PIC_ALIAS(cc_vendor); @@ -172,6 +173,7 @@ static void amd_cc_platform_clear(enum cc_attr attr) switch (attr) { case CC_ATTR_HOST_SEV_SNP: cc_flags.host_sev_snp = 0; + snp_clear_rmpopt_capable(); break; default: break; diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 18c4be75e927..d2cb0a7cd0a2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -761,6 +761,9 @@ #define MSR_AMD64_SEG_RMP_ENABLED_BIT 0 #define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT) #define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8) +#define MSR_AMD64_RMPOPT_BASE 0xc0010139 +#define MSR_AMD64_RMPOPT_ENABLE_BIT 0 +#define MSR_AMD64_RMPOPT_ENABLE BIT_ULL(MSR_AMD64_RMPOPT_ENABLE_BIT) #define MSR_SVSM_CAA 0xc001f000 diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 594cfa19cbd4..0243989f229b 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -662,6 +662,8 @@ static inline void snp_leak_pages(u64 pfn, unsigned int pages) __snp_leak_pages(pfn, pages, true); } int snp_prepare(void); +void snp_setup_rmpopt(void); +void snp_clear_rmpopt_capable(void); void snp_shutdown(void); #else static inline bool snp_probe_rmptable_info(void) { return false; } @@ -680,6 +682,8 @@ static inline void snp_leak_pages(u64 pfn, unsigned int npages) {} static inline void kdump_sev_callback(void) { } static inline void snp_fixup_e820_tables(void) {} static inline int snp_prepare(void) { return -ENODEV; } +static inline void snp_setup_rmpopt(void) {} +static inline void snp_clear_rmpopt_capable(void) {} static inline void snp_shutdown(void) {} #endif diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index 8bcdce98f6dc..dab6e1c290bc 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -124,6 +124,10 @@ static void *rmp_bookkeeping __ro_after_init; static u64 probed_rmp_base, probed_rmp_size; +static cpumask_var_t rmpopt_cpumask; +static phys_addr_t rmpopt_pa_start; +static bool rmpopt_capable; + static LIST_HEAD(snp_leaked_pages_list); static DEFINE_SPINLOCK(snp_leaked_pages_list_lock); @@ -490,6 +494,11 @@ static bool __init setup_rmptable(void) if (rmp_cfg & MSR_AMD64_SEG_RMP_ENABLED) { if (!setup_segmented_rmptable()) return false; + /* + * RMPOPT requires a segmented RMP, so indicate that the + * system is capable of configuring and running RMPOPT. + */ + rmpopt_capable = true; } else { if (!setup_contiguous_rmptable()) return false; @@ -555,6 +564,19 @@ int snp_prepare(void) } EXPORT_SYMBOL_FOR_MODULES(snp_prepare, "ccp"); +static void rmpopt_cleanup(void) +{ + int cpu; + + scoped_guard(cpus_read_lock) { + for_each_cpu(cpu, rmpopt_cpumask) + wrmsrq_on_cpu(cpu, MSR_AMD64_RMPOPT_BASE, 0); + } + + free_cpumask_var(rmpopt_cpumask); + rmpopt_pa_start = 0; +} + void snp_shutdown(void) { u64 syscfg; @@ -563,11 +585,59 @@ void snp_shutdown(void) if (syscfg & MSR_AMD64_SYSCFG_SNP_EN) return; + rmpopt_cleanup(); + clear_rmp(); on_each_cpu(mfd_reconfigure, NULL, 1); } EXPORT_SYMBOL_FOR_MODULES(snp_shutdown, "ccp"); +void snp_clear_rmpopt_capable(void) +{ + rmpopt_capable = false; +} + +void snp_setup_rmpopt(void) +{ + u64 rmpopt_base; + int cpu; + + if (!cpu_feature_enabled(X86_FEATURE_RMPOPT) || !rmpopt_capable) + return; + + if (!zalloc_cpumask_var(&rmpopt_cpumask, GFP_KERNEL)) { + pr_err("Failed to allocate RMPOPT cpumask\n"); + return; + } + + /* + * The RMPOPT_BASE MSR is per-core, so only one thread per core needs + * to set up the RMPOPT_BASE MSR. + * + * Note: only online primary threads are included. If a core's + * primary thread is offline, that core is not covered. CPU hotplug + * is not currently supported with SNP enabled. + */ + scoped_guard(cpus_read_lock) { + for_each_online_cpu(cpu) + if (topology_is_primary_thread(cpu)) + cpumask_set_cpu(cpu, rmpopt_cpumask); + + rmpopt_pa_start = ALIGN_DOWN(PFN_PHYS(min_low_pfn), SZ_1G); + rmpopt_base = rmpopt_pa_start | MSR_AMD64_RMPOPT_ENABLE; + + /* + * Per-CPU RMPOPT tables support at most 2 TB of addressable memory + * for RMP optimizations. Initialize the per-CPU RMPOPT table base + * to the starting physical address to enable RMP optimizations for + * up to 2 TB of system RAM on all CPUs. + */ + for_each_cpu(cpu, rmpopt_cpumask) + wrmsrq_on_cpu(cpu, MSR_AMD64_RMPOPT_BASE, rmpopt_base); + } +} +EXPORT_SYMBOL_FOR_MODULES(snp_setup_rmpopt, "ccp"); + /* * Do the necessary preparations which are verified by the firmware as * described in the SNP_INIT_EX firmware command description in the SNP diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index ca473ca198b8..c002a7ca26a8 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -1477,6 +1477,9 @@ static int __sev_snp_init_locked(int *error, unsigned int max_snp_asid) } snp_hv_fixed_pages_state_update(sev, HV_FIXED); + + snp_setup_rmpopt(); + sev->snp_initialized = true; dev_dbg(sev->dev, "SEV-SNP firmware initialized, SEV-TIO is %s\n", data.tio_en ? "enabled" : "disabled"); -- 2.43.0