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Thu, 24 Apr 2025 05:10:27 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53O5AQik000529 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 05:10:26 GMT Received: from [10.239.29.178] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 23 Apr 2025 22:10:22 -0700 Message-ID: <854259d9-c9e6-4b25-8787-0999099bbf4d@quicinc.com> Date: Thu, 24 Apr 2025 13:09:59 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] PCI: dwc: Set PORT_LOGIC_LINK_WIDTH to one lane To: "Wenbin Yao (Consultant)" , Niklas Cassel CC: , , , , , , , , , , , References: <20250422103623.462277-1-quic_wenbyao@quicinc.com> Content-Language: en-US From: Qiang Yu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 74Rsdrto-fSODPcKzVf1pO7S-VLDt8Xi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDAzMCBTYWx0ZWRfX7PP8Yfr33IBz +t4FKfkbJvE9NcGu/gnOrok+a1AQNUQjnSZ06HOtPromcgx8YVeed5IINrceyIEybe5rCw+A3M5 m45afVdpkosWmY93mp+yDqsb5dMP+MoBaii24VYkXnPmmNEhmxnvqf3wW8ZdyUYe23LapfRymNt PCSc8E9Myg+GdhnKUwqdnovHsRk+IeQNub0bi+jl2YSLc8hdHDHBdE/sXWLNRG88ZSzaZ460fxk XIbNEAEfFkUGPYauiRdVafk5V3sPgA3YLwBDGiLztsqfLv1IP72oXcfLS66TfWYFGfsbYOPiZmc 59za+7omOmQYA9uPSbLMMcg+5MnjPkKEMMUoyGj9qYLLpx1b6Py6pFVijYZ8nCHFwx9J5o+02t6 06TK2h1r0Fa+Hevblu1zDc3r3lcYx94kRr7qEqFH+18xOAKUDTo1d9j3kQvsTnvrMu5T0ClA X-Authority-Analysis: v=2.4 cv=ELgG00ZC c=1 sm=1 tr=0 ts=6809c7c3 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=tzRSLQwXOsdqKkk70FoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 74Rsdrto-fSODPcKzVf1pO7S-VLDt8Xi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_01,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1011 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240030 On 4/24/2025 10:49 AM, Wenbin Yao (Consultant) wrote: > On 4/23/2025 9:24 PM, Niklas Cassel wrote: >> On Tue, Apr 22, 2025 at 06:36:23PM +0800, Wenbin Yao wrote: >>> As per DWC PCIe registers description 4.30a, section 1.13.43, >>> NUM_OF_LANES >>> named as PORT_LOGIC_LINK_WIDTH in PCIe DWC driver, is referred to as >>> the >>> "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express >>> Base 3.0 Specification, revision 1.0. This section explains the >>> conditions >>> need be satisfied for entering Polling.Configuration: >>> >>> "Next state is Polling.Configuration after at least 1024 TS1 Ordered >>> Sets >>> were transmitted, and all Lanes that detected a Receiver during Detect >>> receive eight consecutive training sequences. >>> >>> Otherwise, after a 24 ms timeout the next state is: >>> Polling.Configuration if >>> (i) Any Lane, which detected a Receiver during Detect, received eight >>> consecutive training sequences and a minimum of 1024 TS1 Ordered >>> Sets are >>> transmitted after receiving one TS1 or TS2 Ordered Set. >>> And >>> (ii) At least a predetermined set of Lanes that detected a Receiver >>> during >>> Detect have detected an exit from Electrical Idle at least once since >>> entering Polling.Active. >>> >>> Note: This may prevent one or more bad Receivers or Transmitters from >>> holding up a valid Link from being configured, and allow for additional >>> training in Polling.Configuration. The exact set of predetermined >>> Lanes is >>> implementation specific. >>> >>> Note: Any Lane that receives eight consecutive TS1 or TS2 Ordered Sets >>> should have detected an exit from Electrical Idle at least once since >>> entering Polling.Active." >>> >>> In a PCIe link that supports multiple lanes, if >>> PORT_LOGIC_LINK_WIDTH is >>> set to lane width hardware supports, all lanes that detect a receiver >>> during the Detect phase must receive eight consecutive training >>> sequences. >>> Otherwise, the LTSSM cannot enter Polling.Configuration and link >>> training >>> will fail. >>> >>> Therefore, always set PORT_LOGIC_LINK_WIDTH to 1, regardless of the >>> number >>> of lanes the port actually supports, to make linking up more robust. >>> This >>> setting will not affect the intended link width if all lanes are >>> functional. Additionally, the link can still be established with at >>> least >>> one lane if other lanes are faulty. >>> >>> Co-developed-by: Qiang Yu >>> Signed-off-by: Qiang Yu >>> Signed-off-by: Wenbin Yao >>> --- >>> Changes in v2: >>> - Reword commit message. >>> - Link to v1: >>> https://lore.kernel.org/all/1524e971-8433-1e2d-b39e-65bad0d6c6ce@quicinc.com/ >>> >>>   drivers/pci/controller/dwc/pcie-designware.c | 5 +---- >>>   1 file changed, 1 insertion(+), 4 deletions(-) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-designware.c >>> b/drivers/pci/controller/dwc/pcie-designware.c >>> index 97d76d3dc..be348b341 100644 >>> --- a/drivers/pci/controller/dwc/pcie-designware.c >>> +++ b/drivers/pci/controller/dwc/pcie-designware.c >>> @@ -797,22 +797,19 @@ static void >>> dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) >>>       /* Set link width speed control register */ >>>       lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); >>>       lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK; >>> +    lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; >>>       switch (num_lanes) { >>>       case 1: >>>           plc |= PORT_LINK_MODE_1_LANES; >>> -        lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; >>>           break; >>>       case 2: >>>           plc |= PORT_LINK_MODE_2_LANES; >>> -        lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES; >>>           break; >>>       case 4: >>>           plc |= PORT_LINK_MODE_4_LANES; >>> -        lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES; >>>           break; >>>       case 8: >>>           plc |= PORT_LINK_MODE_8_LANES; >>> -        lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES; >>>           break; >>>       default: >>>           dev_err(pci->dev, "num-lanes %u: invalid value\n", >>> num_lanes); >>> -- >>> 2.34.1 >>> >> I still see the link to my EP (which also have this patch) using all >> four lanes according to lspci, so: >> >> Tested-by: Niklas Cassel Thank you, Niklas, for kindly testing this patch and providing feedback. Wenbin seems to have misunderstood you; sorry for this. > > This setting will not affect the intended link width if all lanes are > functional. Additionally, the link can still be established with at least > one lane if other lanes are faulty. > -- With best wishes Qiang Yu