From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ACC33B7A8; Mon, 23 Dec 2024 16:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734971955; cv=none; b=p0xkEj6TkST8/dvM22V2tG88xz8aVH0Y/l0RGIoWHOvUZgl1FPYgAVkYiqT0OdEuNXvT/e6i1VNb5tGkLoKKK/ltdaKeArhtGtmVaYLRzWkdgoCySlDUbY/xpkSJZ/6Rm7+sXxxEV3EW53wcYz0L8XCxO9scC8t0BTsllqLcQW8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734971955; c=relaxed/simple; bh=35KQeJOKwdFepWTkT6JRbqFbbopLPhFHAchljzxBXLE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XZlRagHI46BvcZ6GnqwZGbhw1WUatEkJFqLgywcPgygxekh49knF7SF9g0YY6KonerrpUaNBlo70fT8OWMf1yKhPPMTso4kUqYKwtfSx1cBtBwhGVZL2amPmxSjEVnUxCGXbw4P2DsCMx1Dl6/VOlnGOIPe/KhwvMGnUH60zWA8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N8HcjNGv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N8HcjNGv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D57CC4CED3; Mon, 23 Dec 2024 16:39:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734971953; bh=35KQeJOKwdFepWTkT6JRbqFbbopLPhFHAchljzxBXLE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=N8HcjNGvtkZHL3tc8H4WTvFtrp+IEautC8kZG9BQ6Vi1keEJUAooKZQLBsKhGR2xe x4r0tZrRgcA75GVecYI3vIXVfRB9S9xltBeUwXkrctyekjMVWvLxQA+i8hlFdbJoVt EvVHe3uSYel9lyqc6fDE8Dov2WWPBoZIY8aLceKw3TjaVj9lG1Zg+8hfGdA829tPC3 RFTWfyvCC6yAOaAuTG+johEI9HrSHzSu2vsiCVPmJWpGuILMwAfjV8Da/O3qvaXn52 NVGHaLoXPtACwYyw+OfmsnFU9rJBDi25vDPehWODJ6sqcLmgoAeTbiduR2u93lP3py yLqFmfkHMY3QQ== Message-ID: <854c8108-261c-4585-be2e-d50758f3a777@kernel.org> Date: Mon, 23 Dec 2024 17:39:08 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] arm64: dts: morello: Add support for common functionalities To: Vincenzo Frascino , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King References: <20241223162029.326997-1-vincenzo.frascino@arm.com> <20241223162029.326997-3-vincenzo.frascino@arm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 23/12/2024 17:20, Vincenzo Frascino wrote: > The Morello architecture is an experimental extension to Armv8.2-A, > which extends the AArch64 state with the principles proposed in > version 7 of the Capability Hardware Enhanced RISC Instructions > (CHERI) ISA. > > The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share > some functionalities that have conveniently been included in > morello.dtsi to avoid duplication. > > Introduce morello.dtsi. > > Note: Morello fvp will be introduced with a future patch series. > > Cc: Linus Walleij > Cc: Rob Herring > Cc: Krzysztof Kozlowski > Cc: Conor Dooley > Cc: Liviu Dudau > Cc: Sudeep Holla > Cc: Lorenzo Pieralisi > Cc: Russell King > Signed-off-by: Vincenzo Frascino > --- > arch/arm64/boot/dts/arm/morello.dtsi | 271 +++++++++++++++++++++++++++ > 1 file changed, 271 insertions(+) > create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi > > diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi > new file mode 100644 > index 000000000000..b9030007d9e6 > --- /dev/null > +++ b/arch/arm64/boot/dts/arm/morello.dtsi > @@ -0,0 +1,271 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. > + */ > + > +#include > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + > + aliases { > + serial0 = &uart0; This belongs to DTS file. > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; As well. > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + secure-firmware@ff000000 { > + reg = <0 0xff000000 0 0x01000000>; > + no-map; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; Blank line > + cpu0: cpu0@0 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x0>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 0>; > + }; Blank line between each device node. > + cpu1: cpu1@100 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x100>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 0>; > + }; > + cpu2: cpu2@10000 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x10000>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 1>; > + }; > + cpu3: cpu3@10100 { > + compatible = "arm,neoverse-n1"; > + reg = <0x0 0x10100>; > + device_type = "cpu"; > + enable-method = "psci"; > + clocks = <&scmi_dvfs 1>; > + }; > + }; > + > + /* The first bank of memory, memory map is actually provided by UEFI. */ > + memory@80000000 { > + device_type = "memory"; > + /* [0x80000000-0xffffffff] */ > + reg = <0x00000000 0x80000000 0x0 0x7F000000>; > + }; > + > + memory@8080000000 { > + device_type = "memory"; > + /* [0x8080000000-0x83f7ffffff] */ > + reg = <0x00000080 0x80000000 0x3 0x78000000>; > + }; > + > + gic: interrupt-controller@2c010000 { You need 'soc' node. ARM DTS files have this unusual, I don't understand why these were done like that. Don't use them as example. Take some latest qcom (sm8650.dtsi) as an example. > + compatible = "arm,gic-v3"; > + #address-cells = <2>; > + #interrupt-cells = <3>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + }; > + > + spe-pmu { > + compatible = "arm,statistical-profiling-extension-v1"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > + > + soc_refclk50mhz: clock-50000000 { Keep nodes ordered by name. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + clock-output-names = "apb_pclk"; > + }; > + > + soc_refclk85mhz: clock-85000000 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <85000000>; > + clock-output-names = "iofpga:aclk"; > + }; > + > + soc_uartclk: clock-50000000-uart { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + clock-output-names = "uartclk"; > + }; > + > + soc: soc { Ah, so here is the soc. GIC should be inside. > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + ranges; > + > + mailbox: mhu@45000000 { > + compatible = "arm,mhu-doorbell", "arm,primecell"; > + reg = <0x0 0x45000000 0x0 0x1000>; > + interrupts = , > + ; Misaligned. It should be aligned to previous < > + #mbox-cells = <2>; > + clocks = <&soc_refclk50mhz>; > + clock-names = "apb_pclk"; > + }; > + > + sram: sram@45200000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x06000000 0x0 0x8000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x06000000 0x8000>; Ranges go immediately after reg (see DTS coding style) > + > + cpu_scp_hpri0: scp-sram@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x80>; > + }; > + > + cpu_scp_hpri1: scp-sram@80 { > + compatible = "arm,scmi-shmem"; > + reg = <0x80 0x80>; > + }; > + }; > + > + uart0: serial@2a400000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0x2a400000 0x0 0x1000>; > + interrupts = ; > + clocks = <&soc_uartclk>, <&soc_refclk50mhz>; > + clock-names = "uartclk", "apb_pclk"; This should be disabled and board should enable it. > + }; > + > + smmu_pcie: iommu@4f400000 { > + compatible = "arm,smmu-v3"; > + reg = <0 0x4f400000 0 0x40000>; > + interrupts = , > + , > + , > + ; > + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; > + msi-parent = <&its2 0>; > + #iommu-cells = <1>; > + dma-coherent; > + }; > + > + pcie_ctlr: pcie@28c0000000 { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + reg = <0x28 0xC0000000 0 0x10000000>; > + bus-range = <0 255>; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + dma-coherent; > + ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, > + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, > + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; > + msi-map = <0 &its_pcie 0 0x10000>; > + iommu-map = <0 &smmu_pcie 0 0x10000>; > + status = "okay"; > + }; > + > + smmu_ccix: iommu@4f000000 { > + compatible = "arm,smmu-v3"; > + reg = <0 0x4f000000 0 0x40000>; > + interrupts = , > + , > + , > + ; > + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; > + msi-parent = <&its1 0>; > + #iommu-cells = <1>; > + dma-coherent; > + }; > + > + ccix_pcie_ctlr: pcie@4fc0000000 { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + reg = <0x4F 0xC0000000 0 0x10000000>; > + bus-range = <0 255>; > + linux,pci-domain = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + dma-coherent; > + ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, > + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, > + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; > + msi-map = <0 &its_ccix 0 0x10000>; > + iommu-map = <0 &smmu_ccix 0 0x10000>; > + status = "okay"; Drop, everywhere > + }; > + > + firmware { firmware is not part of soc. > + #address-cells = <2>; > + #size-cells = <2>; Drop both > + interrupt-parent = <&gic>; > + ranges; Drop ranges, this is all odd. > + > + scmi { > + compatible = "arm,scmi"; > + mbox-names = "tx", "rx"; > + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; > + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; > + #address-cells = <1>; > + #size-cells = <0>; > + scmi_dvfs: protocol@13 { > + reg = <0x13>; > + #clock-cells = <1>; > + }; > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > + }; > + }; > + }; > +}; Best regards, Krzysztof