Re: [PATCH 3/3] MIPS: perf: Add SB1 and SB1A performance counter support

[Randy Dunlap <rdunlap@infradead.org>]

Hi,
This has one 'make htmldocs' warning (see below).

On 11/12/26 11:09 AM, Florian Fainelli wrote:

> ---
>  Documentation/arch/mips/index.rst    |   1 +
>  Documentation/arch/mips/sb1-pmu.rst  | 162 ++++++++++++
>  arch/mips/kernel/perf_event_mipsxx.c | 373 ++++++++++++++++++++++++++-
>  include/linux/cpuhotplug.h           |   1 +
>  4 files changed, 526 insertions(+), 11 deletions(-)
>  create mode 100644 Documentation/arch/mips/sb1-pmu.rst
> 

> diff --git a/Documentation/arch/mips/sb1-pmu.rst b/Documentation/arch/mips/sb1-pmu.rst
> new file mode 100644
> index 000000000000..d589a6262c65
> --- /dev/null
> +++ b/Documentation/arch/mips/sb1-pmu.rst
> @@ -0,0 +1,162 @@

> +Counter selection and mode filtering
> +-----------------------------------

Documentation/arch/mips/sb1-pmu.rst:57: WARNING: Title underline too short.

Counter selection and mode filtering
----------------------------------- [docutils]

> +
> +The ``counter`` format field selects a physical counter: 0 means automatic,
> +and values 1 through 4 select physical counters 0 through 3.  A non-cycle
> +event requesting physical counter 0 is rejected.  Automatic events may move
> +to another eligible counter when a fixed-counter event is added, preserving
> +their accumulated counts and sample periods.


-- 
~Randy