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Thu, 09 Jul 2026 08:28:12 -0700 (PDT) X-Received: by 2002:a17:90b:1d44:b0:37f:d9dc:557 with SMTP id 98e67ed59e1d1-38940638b51mr9374988a91.16.1783610891627; Thu, 09 Jul 2026 08:28:11 -0700 (PDT) Received: from [10.204.66.221] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31198cb2b99sm13681204eec.26.2026.07.09.08.28.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jul 2026 08:28:11 -0700 (PDT) Message-ID: <85a05836-6298-4111-97ca-80d7e3b3a9c4@oss.qualcomm.com> Date: Thu, 9 Jul 2026 20:58:02 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 2/6] dt-bindings: media: qcom,x1e80100-camss: Describe iommu entries To: Bryan O'Donoghue , Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy , Loic Poulain Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Krzysztof Kozlowski , Krzysztof Kozlowski References: <20260708-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v12-0-f8588da41f16@linaro.org> <20260708-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v12-2-f8588da41f16@linaro.org> Content-Language: en-US From: Vikram Sharma In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA5MDE1MiBTYWx0ZWRfX46NIAV9P/Auy 2n6Q5Sc2vB1jIdsQwZELajeIhvW6Pm30BD/Lb7cAgaTJPt3j/XMLawU9RWWbC+BoB8wUnNELnvu ulfF4hm3VJPCqyztYZAAo+SEdLGgAjc= X-Proofpoint-ORIG-GUID: rhvZek5MrCyud4AtNrhhBWy9-EYN7QA4 X-Authority-Analysis: v=2.4 cv=cOLQdFeN c=1 sm=1 tr=0 ts=6a4fbe0c cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=HI1v2mgwsAgm2NAubtIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: rhvZek5MrCyud4AtNrhhBWy9-EYN7QA4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA5MDE1MiBTYWx0ZWRfX61XYKSuIXoeI sJslFOCx1WdJqxap9py+VTPCOnhoj/mBYIRIxWoZ9iHMfwdADJSaZGnU5DvNKRt2gW9zSMJR6X+ wNMc562VNP3wGG7NENrG4QrKcmILKHYc31t0zu1bN23/TjYr9jtQ7IbbPmzD9f1i+trwI2Rp2oM ujujyoxJjWVDNUG6MvtzUbDy+/v43W+Suu5gVUdHQoF2a1xwiJk6XpqyYbmVWDhZqscTzToI/MX DH6t7vqE64y4AoSKAdtYiKrMjJgOMBvcbOnOYc9YB3XzMf4/iDTRj8oGmgUYUnNubWucoelquVx ie46lQF/EtObHN0K6rpSUStyzD8mgXUAZgrpWMSpRxlFAndjTXrM5qr1gf3fRbYRs4W0vUPtF5v eB1SV1bZ48TfnkX60Qzy6esSSw5rP+ALX6UX+rqxj0rsV6usNRMlj2qRJD/TNFA6D1oMu/TlNMj O4DSv9w2L2duiS6yUVA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-09_03,2026-07-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607090152 On 7/9/2026 3:02 AM, Bryan O'Donoghue wrote: > On 08/07/2026 16:15, Vikram Sharma wrote: >> >> On 7/8/2026 5:36 AM, Bryan O'Donoghue wrote: >>>               iommus = <&apps_smmu 0x800 0x60>, >>> +                     <&apps_smmu 0x820 0x60>, >>> +                     <&apps_smmu 0x840 0x60>, >>>                        <&apps_smmu 0x860 0x60>, >> >> I think only "iommus = <&apps_smmu 0x800 0x60>" should be enough as mask which 0x60 is implicitly covering sids like 0x820, 0x840 and 0x860. >> >> Regards, >> Vikram >> > > These all come from the Hamoa iommu defintions in qcom docs. > > Can you double check for yourself and let me know.  Hi Bryan, Confirmed — all four SIDs (0x800, 0x820, 0x840, 0x860) are valid and documented for IFE/SFE. My point was specifically about how the ARM SMMU SMR matching logic handles these with the given mask. In SMR hardware, the mask field marks bits as "don't care" during stream ID comparison. With SID = 0x800 and MASK = 0x60: MASK = 0x60 = 0b 0110 0000  →  bits [6:5] are don't-care The four SIDs differ only in bits [6:5]: 0x800 = 0b 1000 0000 0000  → bits[6:5] = 00 0x820 = 0b 1000 0010 0000  → bits[6:5] = 01 0x840 = 0b 1000 0100 0000  → bits[6:5] = 10 0x860 = 0b 1000 0110 0000  → bits[6:5] = 11 Since 0x60 masks out exactly those differing bits, a single entry <&apps_smmu 0x800 0x60> will match all four SIDs. That said, I'd say this is more of a preference — both forms are functionally correct, and if you prefer keeping the four explicit entries for clarity or to stay aligned with how the Qcom docs enumerate them, that's perfectly fine too. Regards, Vikram