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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bcce8fa10sm28728852b3a.52.2025.08.12.01.19.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Aug 2025 01:19:18 -0700 (PDT) Message-ID: <85dc8b0e-bf0b-44c7-9ef8-cce460fd1d22@oss.qualcomm.com> Date: Tue, 12 Aug 2025 16:19:15 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] coresight-etm4x: Conditionally access register TRCEXTINSELR To: James Clark Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin References: <20250811-trcextinselr_issue-v1-1-ed78f3215502@oss.qualcomm.com> Content-Language: en-US From: yuanfang zhang In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=bY5rUPPB c=1 sm=1 tr=0 ts=689af908 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=bRSsP4KCScyoyIGQGosA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: x3FZZMzR9FlOq3Qpixeee1N-DLu1B-JJ X-Proofpoint-ORIG-GUID: x3FZZMzR9FlOq3Qpixeee1N-DLu1B-JJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA5MDAwMCBTYWx0ZWRfX3tEB9cy26EBb e1Wkm3zVu8agSPKCvtbogUv5kw/qJ+1SH8fR1VRvDL5y9xkgiVmWyljiqHpud4Ymwe/3jq+EkT3 6N4g1Gv2AvAEXLzABuDuUPI5m2v4mop+10ukcUHjJK4WSIpaDGK4gYjDd/i4Xl/9QXGzDgzu1id bHK0wDy/DMROSamL/xJXl5aaZL1ZeOL+AQXGqlZmsKhwRALeUlnfFCOv86H854oRQcqOtpeHBZ7 FRPWBz5hcc5QXnPb4RnghQpF9NmZb85LyqFZMkjiVunST89vzptgneSQmHDl799hKMRb124CAEo NBD2ZAnIISnAGqbfR5YMs5O45pEK24V1IbprtnUEUGwemaFzvHk8ibEF/Re8P+yv0WyS9R4crDu mFNC7tZG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_04,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508090000 On 8/11/2025 6:25 PM, James Clark wrote: > > > On 11/08/2025 10:57 am, Yuanfang Zhang wrote: >> The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. >> To avoid invalid accesses, introduce a check on numextinsel >> (derived from TRCIDR5[11:9]) before reading or writing to this register. >> > > Looks like this should have a fixes: tag. updated in next patch. > >> Signed-off-by: Yuanfang Zhang >> --- >>   drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- >>   drivers/hwtracing/coresight/coresight-etm4x.h      |  2 ++ >>   2 files changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 42e5d37403addc6ec81f2e3184522d67d1677c04..8a9c4caceff0165e4fce7ac4250f3e16ccc1d34e 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) >>           etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >>           etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >>       } >> -    etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); >> +    if (drvdata->numextinsel) >> +        etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); >>       for (i = 0; i < drvdata->nr_cntr; i++) { >>           etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); >>           etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); >> @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) >>       etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); >>       /* NUMEXTIN, bits[8:0] number of external inputs implemented */ >>       drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); >> +    drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); >>       /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ >>       drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); >>       /* ATBTRIG, bit[22] implementation can support ATB triggers? */ >> @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) >>           state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >>           state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >>       } >> -    state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); >> + >> +    if (drvdata->nrseqstate) > > Shouldn't this be "if (drvdata->numextinsel)"? Or it needs a comment saying why it's different to the others. typo, will correct in next patch. > > Otherwise looks ok. > >> +        state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); >>         for (i = 0; i < drvdata->nr_cntr; i++) { >>           state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); >> @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) >>           etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >>           etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >>       } >> -    etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); >> +    if (drvdata->numextinsel) >> +        etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); >>         for (i = 0; i < drvdata->nr_cntr; i++) { >>           etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -162,6 +162,7 @@ >>   #define TRCIDR4_NUMVMIDC_MASK            GENMASK(31, 28) >>     #define TRCIDR5_NUMEXTIN_MASK            GENMASK(8, 0) >> +#define TRCIDR5_NUMEXTINSEL_MASK               GENMASK(11, 9) >>   #define TRCIDR5_TRACEIDSIZE_MASK        GENMASK(21, 16) >>   #define TRCIDR5_ATBTRIG                BIT(22) >>   #define TRCIDR5_LPOVERRIDE            BIT(23) >> @@ -999,6 +1000,7 @@ struct etmv4_drvdata { >>       u8                nr_cntr; >>       u8                nr_ext_inp; >>       u8                numcidc; >> +    u8                numextinsel; >>       u8                numvmidc; >>       u8                nrseqstate; >>       u8                nr_event; >> >> --- >> base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 >> change-id: 20250811-trcextinselr_issue-f267afa0e5ed >> >> Best regards, >