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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 14 Feb 2020 11:09:06 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01EB94aI55640210 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 14 Feb 2020 11:09:04 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 787A5A405B; Fri, 14 Feb 2020 11:09:04 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 74ADFA406A; Fri, 14 Feb 2020 11:09:03 +0000 (GMT) Received: from pic2.home (unknown [9.145.28.205]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 14 Feb 2020 11:09:03 +0000 (GMT) Subject: Re: [PATCH v2 05/27] powerpc: Map & release OpenCAPI LPC memory To: "Alastair D'Silva" , alastair@d-silva.org Cc: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Andrew Donnellan , Arnd Bergmann , Greg Kroah-Hartman , Dan Williams , Vishal Verma , Dave Jiang , Keith Busch , Ira Weiny , Andrew Morton , Mauro Carvalho Chehab , "David S. Miller" , Rob Herring , Anton Blanchard , Krzysztof Kozlowski , Mahesh Salgaonkar , Madhavan Srinivasan , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Anju T Sudhakar , Hari Bathini , Thomas Gleixner , Greg Kurz , Nicholas Piggin , Masahiro Yamada , Alexey Kardashevskiy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-nvdimm@lists.01.org, linux-mm@kvack.org References: <20191203034655.51561-1-alastair@au1.ibm.com> <20191203034655.51561-6-alastair@au1.ibm.com> From: Frederic Barrat Date: Fri, 14 Feb 2020 12:09:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20191203034655.51561-6-alastair@au1.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 x-cbid: 20021411-0020-0000-0000-000003AA12A9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20021411-0021-0000-0000-000022020116 Message-Id: <85e5a3d4-bac2-a8fc-8fc7-865be539dc3c@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-02-14_03:2020-02-12,2020-02-14 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=2 mlxlogscore=898 spamscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002140091 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 03/12/2019 à 04:46, Alastair D'Silva a écrit : > From: Alastair D'Silva > > This patch adds platform support to map & release LPC memory. > > Signed-off-by: Alastair D'Silva > --- > arch/powerpc/include/asm/pnv-ocxl.h | 2 ++ > arch/powerpc/platforms/powernv/ocxl.c | 42 +++++++++++++++++++++++++++ > 2 files changed, 44 insertions(+) > > diff --git a/arch/powerpc/include/asm/pnv-ocxl.h b/arch/powerpc/include/asm/pnv-ocxl.h > index 7de82647e761..f8f8ffb48aa8 100644 > --- a/arch/powerpc/include/asm/pnv-ocxl.h > +++ b/arch/powerpc/include/asm/pnv-ocxl.h > @@ -32,5 +32,7 @@ extern int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) > > extern int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr); > extern void pnv_ocxl_free_xive_irq(u32 irq); > +extern u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size); > +extern void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev); > > #endif /* _ASM_PNV_OCXL_H */ > diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c > index 8c65aacda9c8..b56a48daf48c 100644 > --- a/arch/powerpc/platforms/powernv/ocxl.c > +++ b/arch/powerpc/platforms/powernv/ocxl.c > @@ -475,6 +475,48 @@ void pnv_ocxl_spa_release(void *platform_data) > } > EXPORT_SYMBOL_GPL(pnv_ocxl_spa_release); > > +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size) > +{ > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); > + struct pnv_phb *phb = hose->private_data; > + u32 bdfn = pci_dev_id(pdev); > + __be64 base_addr_be64; > + u64 base_addr; > + int rc; > + > + rc = opal_npu_mem_alloc(phb->opal_id, bdfn, size, &base_addr_be64); > + if (rc) { > + dev_warn(&pdev->dev, > + "OPAL could not allocate LPC memory, rc=%d\n", rc); > + return 0; > + } > + > + base_addr = be64_to_cpu(base_addr_be64); > + > + rc = check_hotplug_memory_addressable(base_addr >> PAGE_SHIFT, > + size >> PAGE_SHIFT); check_hotplug_memory_addressable() is only declared if CONFIG_MEMORY_HOTPLUG_SPARSE is selected. I think we also need a #ifdef here. Fred > + if (rc) > + return 0; > + > + return base_addr; > +} > +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_setup); > + > +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev) > +{ > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); > + struct pnv_phb *phb = hose->private_data; > + u32 bdfn = pci_dev_id(pdev); > + int rc; > + > + rc = opal_npu_mem_release(phb->opal_id, bdfn); > + if (rc) > + dev_warn(&pdev->dev, > + "OPAL reported rc=%d when releasing LPC memory\n", rc); > +} > +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_release); > + > + > int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) > { > struct spa_data *data = (struct spa_data *) platform_data; >