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Wed, 14 Oct 2026 09:42:42 -0700 (PDT) X-Received: by 2002:a05:620a:269a:b0:93a:14c:329c with SMTP id af79cd13be357-93ebd0c2693mr3053021385a.1.1791996161600; Wed, 14 Oct 2026 09:42:41 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c3ed963cf98sm4760366b.13.2026.10.14.09.42.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2026 09:42:40 -0700 (PDT) Message-ID: <85f24f78-9b30-4394-9899-65e19eef1b16@oss.qualcomm.com> Date: Wed, 14 Oct 2026 18:42:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH DNM RFC 14/16] clk: qcom: Enable clk-dvfs on SM8650 To: Dmitry Baryshkov Cc: Konrad Dybcio , Stephen Boyd , Brian Masney , Jerome Brunet , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" , Pavel Machek , Len Brown , Greg Kroah-Hartman , Danilo Krummrich , Johan Hovold , Ulf Hansson , Bjorn Andersson , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Mike Tipton , Taniya Das , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, driver-core@lists.linux.dev, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20261014-topic-qc_clk_dvfs-v1-0-3041b788e9f7@oss.qualcomm.com> <20261014-topic-qc_clk_dvfs-v1-14-3041b788e9f7@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: dqf5NTXndhpsQ03vcrqwG-JNXqZ6bCHo X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDA2NiBTYWx0ZWRfX+3iy+db2wXZr +340xgRVN/5XJbfHGxN7SiRi4W0aOtYP54EmKDjguBmNKyby4iVLNtwzLWgugMJT028jIBotXBq K6IxsllYVLFmuBLcYOYDd0HLl/1SUTY= X-Proofpoint-GUID: dqf5NTXndhpsQ03vcrqwG-JNXqZ6bCHo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDA2NiBTYWx0ZWRfX2SMAvS5eTx4C naiwewM5enOFIA4yNwQ81ET1t6w88xtudhfUUzynoMUNKMRptY/yGwMKOlW+W0KeLuU2SoZ7Blv ox47BuHmY0OIvh4lwlyTzf34pv364m2MTXEELfcn7ObRbLiR9ruzkiAT92SeiMPcnzwvoSBF0Rs vCsbVv8XI8/38vIAhWU3uwZtbtnyJZ9BOGd8SIDwY0nI/eS+mMNQIqqxsNdRpwMvvrvBpRihIHO k8hOtdnG4t8QiPVSXN+Z0LgIQZB4yeJIpYR/KmplGO14Atv+knFSwn6Seuhf6KKk+mvGE0RXJIH RziuqoHP+eDd+XQG+jzr61iDkziIlj2X66OWOXwUnPd2ORWtt/JiH1zKr6thjoYXqRdvAsBUvjj VYdEhvc6ZQtOlCJYkqYv8CWFXnl+vrE1E/ajXBkqnse74rfUZZXcp6fsGT1grAaQHi1uwntKTnj sZvK+PxUUgfXg4DfnPQ== X-Authority-Analysis: v=2.4 cv=SYZi5fRu c=1 sm=1 tr=0 ts=6acfb103 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=lNqPBwARffoA8ln7mLoA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140066 On 10/14/26 6:35 PM, Dmitry Baryshkov wrote: > On Wed, Oct 14, 2026 at 05:22:40PM +0200, Konrad Dybcio wrote: >> On 10/14/26 4:40 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 14, 2026 at 02:19:14PM +0200, Konrad Dybcio wrote: >>>> From: Konrad Dybcio >>>> >>>> Make use of the clock-dvfs infrastructure and fill in the power >>>> requirements for SM8650's clocks to ensure the hardware can operate in >>>> accordance with the specification. >> >> [...] >> >>>> #include >>>> +#include >>> >>> I've commented to the cover letter. For me it feels like the layering >>> violation. >> >> I understand. I still think it's okay given this is a driver only >> for a specific SoC. > > Then soon we will get MMRM submitted upstream, which (currently) > randomly imports a set of the clock ids and asks consumers to talk to it > using the same clock IDS from DT bindings. Doesn't sounds like a good > idea. MMRM is more or less clk-powercap. The data it grabs via DT (power numbers) could as well be put into the clock driver here, in a similar fashion. >> [...] >> >>>> +static const struct qcom_clk_dvfs_data cam_cc_camnoc_axi_rt_clk_src_dvfs = { >>>> + .pd_indices = (const unsigned int[]) { DT_PMDOMAIN_MMCX, DT_PMDOMAIN_MXC }, >>>> + .num_pd_indices = 2, >>>> + .rates = (const struct qcom_clk_dvfs_rate[]) { >>>> + { 300000000, RPMH_REGULATOR_LEVEL_LOW_SVS }, >>>> + { 400000000, RPMH_REGULATOR_LEVEL_SVS }, >>> >>> And does it actually have the same vote on both MMCX and MXC? I'd need >>> to check the clock tree. >> >> In this case the RCG needs VDD_MM and its direct child branch >> needs MXC for the flipflops. > > My question was "on the same level? Or on different levels? In the OPP > tables we (should) have 1:1 between scaling PDs and PD votes. On the same level. Konrad