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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 14:59:53.8337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4924d3ba-8477-4084-e0cf-08de2132f8c7 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR10MB7591 On 11/11/25 7:39 PM, Manivannan Sadhasivam wrote: > On Tue, Nov 11, 2025 at 05:09:25PM +0530, Siddharth Vadapalli wrote: >> On Tue, 2025-11-11 at 16:24 +0530, Manivannan Sadhasivam wrote: >> >> Hello Mani, >> >>> + Siddharth >> >> Thank you for notifying me of this. >> >>> >>> On Tue, Nov 11, 2025 at 05:28:54PM +0800, kernel test robot wrote: >>>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master >>>> head: 4427259cc7f7571a157fbc9b5011e1ef6fe0a4a8 >>>> commit: 1c72774df028429836eec3394212f2921bb830fc PCI: sg2042: Add Sophgo SG2042 PCIe driver >>>> date: 8 weeks ago >>>> config: loongarch-randconfig-r113-20251110 (https://download.01.org/0day-ci/archive/20251111/202511111705.MZ7ls8Hm-lkp@intel.com/config) >>>> compiler: loongarch64-linux-gcc (GCC) 15.1.0 >>>> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251111/202511111705.MZ7ls8Hm-lkp@intel.com/reproduce) >>>> >>>> If you fix the issue in a separate patch/commit (i.e. not just a new version of >>>> the same patch/commit), kindly add following tags >>>>> Reported-by: kernel test robot >>>>> Closes: https://lore.kernel.org/oe-kbuild-all/202511111705.MZ7ls8Hm-lkp@intel.com/ >>>> >>>> All errors (new ones prefixed by >>): >>>> >>>> loongarch64-linux-ld: drivers/pci/controller/cadence/pci-j721e.o: in function `j721e_pcie_remove': >>>>>> drivers/pci/controller/cadence/pci-j721e.c:648:(.text+0x83c): undefined reference to `cdns_pcie_host_disable' >>>> >>> >>> From .config: >>> >>> CONFIG_PCIE_CADENCE=y >>> CONFIG_PCIE_CADENCE_HOST=m >>> CONFIG_PCIE_CADENCE_EP=y >>> CONFIG_PCIE_CADENCE_PLAT=y >>> # CONFIG_PCIE_CADENCE_PLAT_HOST is not set >>> CONFIG_PCIE_CADENCE_PLAT_EP=y >>> CONFIG_PCIE_SG2042_HOST=m >>> CONFIG_PCI_J721E=y >>> # CONFIG_PCI_J721E_HOST is not set >>> CONFIG_PCI_J721E_EP=y >>> >>> PCI_J721E selects PCIE_CADENCE_HOST only if PCI_J721E_HOST is selected, >>> otherwise, it will not select it. This will take care of the dependency between >>> PCI_J721E and PCIE_CADENCE_{HOST/EP}. >>> >>> But if PCIE_CADENCE_HOST is selected as a module by other drivers like, >>> CONFIG_PCIE_SG2042_HOST=m, then if PCI_J721E is selected as a built-in using >>> CONFIG_PCI_J721E_EP=y, it results in this build error as the built-in driver >>> becomes dependent on a symbol from a loadable module. >> >> While I don't deny the build error associated with the above config, it is >> an invalid config in the sense that the Glue drivers for two different >> devices are being enabled. This seems to be a generic issue wherein >> multiple drivers tend to depend on a library/common driver. How is it >> handled in such cases? > > AFAIK, the common library should be built-in to avoid issues like this. Ok. If that is the usual approach then I have no objections to it. > >> Is there a notion of reordering configs to ensure that such build errors >> are avoided? >> >> If PCI_J721E_EP was selected as 'y' before 'PCI_SG2042_HOST' being selected >> as 'm', it would have resulted in 'PCIE_CADENCE_EP' being selected as 'y' >> and this won't cause a build error even with 'PCI_SG2042_HOST' selected as >> 'm'. >> >>> >>> I guess, we should force PCIE_CADENCE_{HOST/EP} to be 'bool' as it is getting >>> selected by multiple drivers. >> >> This will defeat the purpose of the series that enabled loadable module >> support for the pci-j721e.c driver and the pcie-cadence-host/ep.c drivers. >> > > Your 'pci-j721e.c' can still be a loadable module, only the common library will > be built-in, which is not that bad. Yes, this will work. Please let me know if you want me to post the patch to update CONFIG_PCIE_CADENCE_{EP/HOST} to a bool. Regards, Siddharth.