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[109.121.139.111]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e7521c9a65sm7537632f8f.17.2025.09.10.07.28.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Sep 2025 07:28:51 -0700 (PDT) Message-ID: <861a0703-2adc-4e8c-86e5-c22192759e80@suse.com> Date: Wed, 10 Sep 2025 17:28:43 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 02/15] x86/mce: Define BSP-only init To: Yazen Ghannam Cc: x86@kernel.org, Tony Luck , "Rafael J. Wysocki" , linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, Smita.KoralahalliChannabasappa@amd.com, Qiuxu Zhuo , linux-acpi@vger.kernel.org References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> <20250908-wip-mca-updates-v6-2-eef5d6c74b9c@amd.com> <98d80660-7140-43a2-b17c-07a0884996f8@suse.com> <20250910135323.GC11602@yaz-khff2.amd.com> Content-Language: en-US From: Nikolay Borisov Autocrypt: addr=nik.borisov@suse.com; keydata= xsFNBGcrpvIBEAD5cAR5+qu30GnmPrK9veWX5RVzzbgtkk9C/EESHy9Yz0+HWgCVRoNyRQsZ 7DW7vE1KhioDLXjDmeu8/0A8u5nFMqv6d1Gt1lb7XzSAYw7uSWXLPEjFBtz9+fBJJLgbYU7G OpTKy6gRr6GaItZze+r04PGWjeyVUuHZuncTO7B2huxcwIk9tFtRX21gVSOOC96HcxSVVA7X N/LLM2EOL7kg4/yDWEhAdLQDChswhmdpHkp5g6ytj9TM8bNlq9I41hl/3cBEeAkxtb/eS5YR 88LBb/2FkcGnhxkGJPNB+4Siku7K8Mk2Y6elnkOctJcDvk29DajYbQnnW4nhfelZuLNupb1O M0912EvzOVI0dIVgR+xtosp66bYTOpX4Xb0fylED9kYGiuEAeoQZaDQ2eICDcHPiaLzh+6cc pkVTB0sXkWHUsPamtPum6/PgWLE9vGI5s+FaqBaqBYDKyvtJfLK4BdZng0Uc3ijycPs3bpbQ bOnK9LD8TYmYaeTenoNILQ7Ut54CCEXkP446skUMKrEo/HabvkykyWqWiIE/UlAYAx9+Ckho TT1d2QsmsAiYYWwjU8igXBecIbC0uRtF/cTfelNGrQwbICUT6kJjcOTpQDaVyIgRSlUMrlNZ XPVEQ6Zq3/aENA8ObhFxE5PLJPizJH6SC89BMKF3zg6SKx0qzQARAQABzSZOaWtvbGF5IEJv cmlzb3YgPG5pay5ib3Jpc292QHN1c2UuY29tPsLBkQQTAQoAOxYhBDuWB8EJLBUZCPjT3SRn XZEnyhfsBQJnK6byAhsDBQsJCAcCAiICBhUKCQgLAgQWAgMBAh4HAheAAAoJECRnXZEnyhfs XbIQAJxuUnelGdXbSbtovBNm+HF3LtT0XnZ0+DoR0DemUGuA1bZAlaOXGr5mvVbTgaoGUQIJ 3Ejx3UBEG7ZSJcfJobB34w1qHEDO0pN9orGIFT9Bic3lqhawD2r85QMcWwjsZH5FhyRx7P2o DTuUClLMO95GuHYQngBF2rHHl8QMJPVKsR18w4IWAhALpEApxa3luyV7pAAqKllfCNt7tmed uKmclf/Sz6qoP75CvEtRbfAOqYgG1Uk9A62C51iAPe35neMre3WGLsdgyMj4/15jPYi+tOUX Tc7AAWgc95LXyPJo8069MOU73htZmgH4OYy+S7f+ArXD7h8lTLT1niff2bCPi6eiAQq6b5CJ Ka4/27IiZo8tm1XjLYmoBmaCovqx5y5Xt2koibIWG3ZGD2I+qRwZ0UohKRH6kKVHGcrmCv0J YO8yIprxgoYmA7gq21BpTqw3D4+8xujn/6LgndLKmGESM1FuY3ymXgj5983eqaxicKpT9iq8 /a1j31tms4azR7+6Dt8H4SagfN6VbJ0luPzobrrNFxUgpjR4ZyQQ++G7oSRdwjfIh1wuCF6/ mDUNcb6/kA0JS9otiC3omfht47yQnvod+MxFk1lTNUu3hePJUwg1vT1te3vO5oln8lkUo9BU knlYpQ7QA2rDEKs+YWqUstr4pDtHzwQ6mo0rqP+zzsFNBGcrpvIBEADGYTFkNVttZkt6e7yA LNkv3Q39zQCt8qe7qkPdlj3CqygVXfw+h7GlcT9fuc4kd7YxFys4/Wd9icj9ZatGMwffONmi LnUotIq2N7+xvc4Xu76wv+QJpiuGEfCDB+VdZOmOzUPlmMkcJc/EDSH4qGogIYRu72uweKEq VfBI43PZIGpGJ7TjS3THX5WVI2YNSmuwqxnQF/iVqDtD2N72ObkBwIf9GnrOgxEyJ/SQq2R0 g7hd6IYk7SOKt1a8ZGCN6hXXKzmM6gHRC8fyWeTqJcK4BKSdX8PzEuYmAJjSfx4w6DoxdK5/ 9sVrNzaVgDHS0ThH/5kNkZ65KNR7K2nk45LT5Crjbg7w5/kKDY6/XiXDx7v/BOR/a+Ryo+lM MffN3XSnAex8cmIhNINl5Z8CAvDLUtItLcbDOv7hdXt6DSyb65CdyY8JwOt6CWno1tdjyDEG 5ANwVPYY878IFkOJLRTJuUd5ltybaSWjKIwjYJfIXuoyzE7OL63856MC/Os8PcLfY7vYY2LB cvKH1qOcs+an86DWX17+dkcKD/YLrpzwvRMur5+kTgVfXcC0TAl39N4YtaCKM/3ugAaVS1Mw MrbyGnGqVMqlCpjnpYREzapSk8XxbO2kYRsZQd8J9ei98OSqgPf8xM7NCULd/xaZLJUydql1 JdSREId2C15jut21aQARAQABwsF2BBgBCgAgFiEEO5YHwQksFRkI+NPdJGddkSfKF+wFAmcr pvICGwwACgkQJGddkSfKF+xuuxAA4F9iQc61wvAOAidktv4Rztn4QKy8TAyGN3M8zYf/A5Zx VcGgX4J4MhRUoPQNrzmVlrrtE2KILHxQZx5eQyPgixPXri42oG5ePEXZoLU5GFRYSPjjTYmP ypyTPN7uoWLfw4TxJqWCGRLsjnkwvyN3R4161Dty4Uhzqp1IkNhl3ifTDYEvbnmHaNvlvvna 7+9jjEBDEFYDMuO/CA8UtoVQXjy5gtOhZZkEsptfwQYc+E9U99yxGofDul7xH41VdXGpIhUj 4wjd3IbgaCiHxxj/M9eM99ybu5asvHyMo3EFPkyWxZsBlUN/riFXGspG4sT0cwOUhG2ZnExv XXhOGKs/y3VGhjZeCDWZ+0ZQHPCL3HUebLxW49wwLxvXU6sLNfYnTJxdqn58Aq4sBXW5Un0Q vfbd9VFV/bKFfvUscYk2UKPi9vgn1hY38IfmsnoS8b0uwDq75IBvup9pYFyNyPf5SutxhFfP JDjakbdjBoYDWVoaPbp5KAQ2VQRiR54lir/inyqGX+dwzPX/F4OHfB5RTiAFLJliCxniKFsM d8eHe88jWjm6/ilx4IlLl9/MdVUGjLpBi18X7ejLz3U2quYD8DBAGzCjy49wJ4Di4qQjblb2 pTXoEyM2L6E604NbDu0VDvHg7EXh1WwmijEu28c/hEB6DwtzslLpBSsJV0s1/jE= In-Reply-To: <20250910135323.GC11602@yaz-khff2.amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10.09.25 г. 16:53 ч., Yazen Ghannam wrote: > On Wed, Sep 10, 2025 at 02:47:16PM +0300, Nikolay Borisov wrote: >> >> >> On 9/8/25 18:40, Yazen Ghannam wrote: >>> Currently, MCA initialization is executed identically on each CPU as >>> they are brought online. However, a number of MCA initialization tasks >>> only need to be done once. >>> >>> Define a function to collect all 'global' init tasks and call this from >>> the BSP only. Start with CPU features. >>> >>> Reviewed-by: Qiuxu Zhuo >>> Tested-by: Tony Luck >>> Reviewed-by: Tony Luck >>> Signed-off-by: Yazen Ghannam >> >> >> >>> @@ -2240,6 +2233,27 @@ DEFINE_IDTENTRY_RAW(exc_machine_check) >>> } >>> #endif >>> +void mca_bsp_init(struct cpuinfo_x86 *c) >>> +{ >>> + u64 cap; >>> + >>> + if (!mce_available(c)) >>> + return; >>> + >>> + mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV); >>> + mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR); >>> + mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA); >>> + >>> + rdmsrq(MSR_IA32_MCG_CAP, cap); >>> + >>> + /* Use accurate RIP reporting if available. */ >>> + if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) >>> + mca_cfg.rip_msr = MSR_IA32_MCG_EIP; >>> + >>> + if (cap & MCG_SER_P) >>> + mca_cfg.ser = 1; >>> +} >>> + >> >> >> LGTM >> >> Reviewed-by: Nikolay Borisov > > Thanks Nikokay for the reviews. > >> >> nit: One question though for those CPUs which consist of P+E cores, is it >> mandated that both types of cores will have identical MCE architecture, I >> assume the x86 world will be a lot more unified than Arm's big.LITTLE ? >> > > I think technically no, they won't be mandated to be identical. We already > have per-CPU feature bits, registers, etc. And in Scalable MCA there are > also per-bank config bits. > > However, this doesn't mean we will have different MCE features between > CPUs in a system just yet. The architects do try to make things flexible > and scalable just in case there is a need in the future. > > We can code to the architectures and be *mostly* future-proof. But it's > not guaranteed to be without bugs. And it's not guaranteed that every > possible case will be used. > > Do you have any concerns or see any issues with the code today in this > area? Maybe you're thinking we should have per-CPU config for feature > bits? If so, I agree but we don't have a real need today AFAIK. Yes, for example in your current code you assume that whatever the value of MSR_IA32_MCG_CAP w.r.t MCG_EXT_P or MCG_SER_P it will be identical for all CPUs. That might be fine, but what if, in the future, we end up with machines where MCG_CAP will have different values for different CPU's/cores. Or that in a system we can end up with cpu's which have different X86_FEATURE_SMCA value. OTOH, you are right that when the time comes we can worry about this since there can possibly be infinite number of possible scenarios. > > Maybe others can comment too. > > Thanks, > Yazen