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rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V1] accel/amdxdna: Poll MPNPU_PWAITMODE after requesting firmware suspend Content-Language: en-US To: Mario Limonciello , , , , CC: , , References: <20251202053717.461943-1-lizhi.hou@amd.com> From: Lizhi Hou In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE16:EE_|MN2PR12MB4285:EE_ X-MS-Office365-Filtering-Correlation-Id: 60bc5a5f-0a2a-45aa-e432-08de31c267a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?c2NXVW5CQ0tGc3ZlVjlOZ2NjelFBT3lPUncvNkJXN0tnOXpZS3Y2NjQ2Mkhs?= =?utf-8?B?NkNmaVM1dGJDOUJIWnJjNzZ1azBZVmpoMi9IN1Zod3FIdTB3Q2JwWFBnZ3Ro?= =?utf-8?B?K0FIQTRzNXFaeVN0Z2lPQk84dEZQQWJNSmpCeXZINU1zL1lQSllWZ0ljUGVM?= =?utf-8?B?d3hXa3E5cDZpZ0MwWitHQUo4b2dEUmh2VldMODRqcUh1V2tKMVJKdFkzVUU5?= =?utf-8?B?VnJRUFNlS1A3UWd2UVE0WHpGN2drRDVyVW4ySzZDc29BWm4zMURFNUZwNENw?= =?utf-8?B?MzYxUC95UTE4YllmbG42bkpOUC80V2JpNlpITU9SclZlZ1p4WXZCNVA1QkVv?= =?utf-8?B?NTJ5TkZKV1VPblZiM2Raay9nZWhSaXdoamJLTUxwY0RHUEU4Z0drcjloTStO?= =?utf-8?B?blNReVcwTlR0T2FXUloxREYva1Nzai9iWW1CVDBmMmFkVGJjMVl3TVdtS0tD?= =?utf-8?B?TnFFS3BvZENmRHh1UDlqL0YrZ0Y2QXJiblNNSlNQUkpnenUxeTRGKy9IbDA1?= =?utf-8?B?WVFtRzUvMURUZmdaVExsYUY5WmpYTjQvY3d5QzRqZ0h1aVkyakZVS3E3cnVJ?= =?utf-8?B?MmJ3bHN2RmgzMzY3TW9pUXBkRnIzODdzcEhSZ1QwOHpwazJFUkIvWEJmaGZR?= =?utf-8?B?QkpHdFRwS2E2QXNlY0ZXRzhqYUVDWWcrWmp4dWs4ZmE1T3V0dm40OEh4WUNw?= =?utf-8?B?L2doWnlwSHNEVDIyb2JLeUlQNXVVc0RBZk1VTm1zbUFRMlhpakRVZXRab1Ux?= =?utf-8?B?VEF6Zmk1TlBkb1dhYnpVV0NzOEliKzdYc3FLZHhidFlOUWU4VXZDcm1ZUHJy?= =?utf-8?B?bmZEbVNONVpoT3JQRGI3elYxVm83cnl0UkU0UVMzMXZyYlV5blJ4M0JVeXNN?= =?utf-8?B?ZmlzVldEamV1RmxRSmNzUFlwRVNQd3BNU1RSVVc4aTdKQUtJYzZZWDVtak5w?= =?utf-8?B?b0pzZlU4WHFKYVV6TElBcWExV0V2OU9Qa1BFNjMwWGNqWVExZE5JcldlNmJn?= =?utf-8?B?VmdacnR5aTVlQVU5T2FRMUE4Z0ZrVUY5T0xlc1RLd0dlcnhGNEh5RWV0MTJT?= =?utf-8?B?ejNoM0JXalRtQVdNU0F5WTBORThmVWhKakpaaEVIUnc0WDZnQjQzUnFKU2NR?= =?utf-8?B?YTFSVUZsamZtenlWT1JCMXhGZzBLR3NRTEhZbWpBRnFCeTZhMmk5UmkxVVRi?= =?utf-8?B?d3NSNXJ4Q2hidjJYQzNBcC9hN09zMTdTKzhxcmtTTVlOZjlrV0RqajJDOEtX?= =?utf-8?B?c0ZsZWZJd1NvS2VCSHFCY1hjL25yTkdnNFlVWDlsTnd4M2QxWHFXVk1LY2xq?= =?utf-8?B?UEFFd0lPR2xQMkIzcVhtS0I3cTIrYzE5OXJmYk5FWEYzT3ZtOVl0enZvV09q?= =?utf-8?B?Q2dpMXFYU1YyYW82aVpUbitwU3oxa0lLZzRTRUFFQ2NZZy9iRGpGaEZEd0p2?= =?utf-8?B?cVh4Mk53eXJnK1ZMQWdnYU9MbnJIZ1RQd0hFL2l6OXpFVGN1Ujl1TDRpa1VC?= =?utf-8?B?WG5DSnFxMHR6bUxmdWZDc1VBV0QwOUd0MGZ1dmRpbFJ6bUlPaUp6RXdWQ29a?= =?utf-8?B?UDBtb2N5OWtrenNKNkhnNVdNLzlpSVRsbTlYYmR5bS9weHVZWXIyTGlBL0tK?= =?utf-8?B?NzU2TGdVWW0zbXQyNFBoM2pDK1ZvVFZqd1hKYTYweVpTZWp1Q3k0RWNWejdp?= =?utf-8?B?cU5udWlQS3FhTmlVWnNCR0FwZjd6MTA2RXozVUJqY29XZjZmSmFpOXJXYjY1?= =?utf-8?B?QjlsZ0ZzRFU0Yks5SGQxdERBU2NMRFZQODUybVFUcGNlS0kwMk10SDY5aC82?= =?utf-8?B?Y3JycDJZZGNSZmE0cXgzSDgrWDAwcDVUdE12dkJ4WmtXeXo3ZFd4dmE5d3Y3?= =?utf-8?B?Mk1vUGhyZDZLOXVMbGNiZnVvMFNoU3VGNzlmSzVaZTZ1K0dxMnFkY0ZDbS9y?= =?utf-8?B?SS9iVUYvOFJGaXBJTUtCSUROVVdsWDduRSs1cmZZN1g4cFRNRjRVZmhzQjRr?= =?utf-8?B?c0tXUlI3a1Y4LzF5S2t3U3BmUWZOaGNEaGQwZkJjU2RzUUZOYVJBSURIdnhM?= =?utf-8?B?bzZwUW03eGt5bDR6cTJmc0ZsSFhRRS93eEpBWmlyTG5LUmdEMWFaT2RiTkZz?= =?utf-8?Q?VmdE=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2025 16:46:56.3986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60bc5a5f-0a2a-45aa-e432-08de31c267a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4285 On 12/1/25 21:51, Mario Limonciello wrote: > > > On 12/1/2025 11:37 PM, Lizhi Hou wrote: >> After issuing a firmware suspend request, the driver must ensure that >> the >> suspend operation has completed before proceeding. Add polling of the >> MPNPU_PWAITMODE register to confirm that the firmware has fully entered >> the suspended state. This prevents race conditions where subsequent >> operations assume the firmware is idle before it has actually completed >> its suspend sequence. >> >> Signed-off-by: Lizhi Hou >> --- >>   drivers/accel/amdxdna/aie2_message.c |  9 ++++++++- >>   drivers/accel/amdxdna/aie2_pci.h     |  2 ++ >>   drivers/accel/amdxdna/aie2_psp.c     | 15 +++++++++++++++ >>   drivers/accel/amdxdna/npu1_regs.c    |  2 ++ >>   drivers/accel/amdxdna/npu2_regs.c    |  2 ++ >>   drivers/accel/amdxdna/npu4_regs.c    |  2 ++ >>   drivers/accel/amdxdna/npu5_regs.c    |  4 +++- >>   drivers/accel/amdxdna/npu6_regs.c    |  2 ++ >>   8 files changed, 36 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/accel/amdxdna/aie2_message.c >> b/drivers/accel/amdxdna/aie2_message.c >> index d493bb1c3360..fee3b0627aba 100644 >> --- a/drivers/accel/amdxdna/aie2_message.c >> +++ b/drivers/accel/amdxdna/aie2_message.c >> @@ -59,8 +59,15 @@ static int aie2_send_mgmt_msg_wait(struct >> amdxdna_dev_hdl *ndev, >>   int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev) >>   { >>       DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND); >> +    int ret; >>   -    return aie2_send_mgmt_msg_wait(ndev, &msg); >> +    ret = aie2_send_mgmt_msg_wait(ndev, &msg); >> +    if (ret) { >> +        XDNA_ERR(ndev->xdna, "Failed to suspend fw, ret %d", ret); >> +        return ret; >> +    } >> + >> +    return aie2_psp_waitmode_poll(ndev->psp_hdl); >>   } >>     int aie2_resume_fw(struct amdxdna_dev_hdl *ndev) >> diff --git a/drivers/accel/amdxdna/aie2_pci.h >> b/drivers/accel/amdxdna/aie2_pci.h >> index a5f9c42155d1..cc9f933f80b2 100644 >> --- a/drivers/accel/amdxdna/aie2_pci.h >> +++ b/drivers/accel/amdxdna/aie2_pci.h >> @@ -70,6 +70,7 @@ enum psp_reg_idx { >>       PSP_INTR_REG = PSP_NUM_IN_REGS, >>       PSP_STATUS_REG, >>       PSP_RESP_REG, >> +    PSP_PWAITMODE_REG, >>       PSP_MAX_REGS /* Keep this at the end */ >>   }; >>   @@ -290,6 +291,7 @@ int aie2_pm_set_mode(struct amdxdna_dev_hdl >> *ndev, enum amdxdna_power_mode_type >>   struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct >> psp_config *conf); >>   int aie2_psp_start(struct psp_device *psp); >>   void aie2_psp_stop(struct psp_device *psp); >> +int aie2_psp_waitmode_poll(struct psp_device *psp); >>     /* aie2_error.c */ >>   int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev); >> diff --git a/drivers/accel/amdxdna/aie2_psp.c >> b/drivers/accel/amdxdna/aie2_psp.c >> index f28a060a8810..4bc60f458fd4 100644 >> --- a/drivers/accel/amdxdna/aie2_psp.c >> +++ b/drivers/accel/amdxdna/aie2_psp.c >> @@ -76,6 +76,21 @@ static int psp_exec(struct psp_device *psp, u32 >> *reg_vals) >>       return 0; >>   } >>   +int aie2_psp_waitmode_poll(struct psp_device *psp) >> +{ >> +    int mode_reg = -1, ret; > > It seems like from the usage mode_reg shouldn't be a signed integer. Will change it to u32. > >> + >> +    ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), >> mode_reg, >> +                 (mode_reg & 0x1) == 1, >> +                 PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); >> +    if (ret) { >> +        drm_err(psp->ddev, "fw waitmode reg error, ret 0x%x", ret); > > Aren't these return codes going to be negative in the case of an > error? IE they shouldn't be 0x%x, they should be %d. Agree. I will fix this. > > Also shouldn't you be using XDNA_ERR()? Sure. I can use XDNA_ERR. > >> +        return ret; >> +    } >> + >> +    return 0; > > You can probably simplify as: > > if (ret) >     drm_err(); > return ret; Agree. > >> +} >> + >>   void aie2_psp_stop(struct psp_device *psp) >>   { >>       u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, }; >> diff --git a/drivers/accel/amdxdna/npu1_regs.c >> b/drivers/accel/amdxdna/npu1_regs.c >> index ec407f3b48fc..ebc6e2802297 100644 >> --- a/drivers/accel/amdxdna/npu1_regs.c >> +++ b/drivers/accel/amdxdna/npu1_regs.c >> @@ -13,6 +13,7 @@ >>   #include "amdxdna_pci_drv.h" >>     /* Address definition from NPU1 docs */ >> +#define MPNPU_PWAITMODE            0x3010034 >>   #define MPNPU_PUB_SEC_INTR        0x3010090 >>   #define MPNPU_PUB_PWRMGMT_INTR        0x3010094 >>   #define MPNPU_PUB_SCRATCH2        0x30100A0 >> @@ -92,6 +93,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = { >>           DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU1_PSP, >> MPNPU_PUB_SEC_INTR), >>           DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, >> MPNPU_PUB_SCRATCH2), >>           DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU1_PSP, >> MPNPU_PUB_SCRATCH3), >> +        DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU1_PSP, >> MPNPU_PWAITMODE), >>       }, >>       .smu_regs_off   = { >>           DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH5), >> diff --git a/drivers/accel/amdxdna/npu2_regs.c >> b/drivers/accel/amdxdna/npu2_regs.c >> index 86f87d0d1354..ad0743fb06d5 100644 >> --- a/drivers/accel/amdxdna/npu2_regs.c >> +++ b/drivers/accel/amdxdna/npu2_regs.c >> @@ -13,6 +13,7 @@ >>   #include "amdxdna_pci_drv.h" >>     /* NPU Public Registers on MpNPUAxiXbar (refer to Diag >> npu_registers.h) */ >> +#define MPNPU_PWAITMODE                0x301003C >>   #define MPNPU_PUB_SEC_INTR             0x3010060 >>   #define MPNPU_PUB_PWRMGMT_INTR         0x3010064 >>   #define MPNPU_PUB_SCRATCH0             0x301006C >> @@ -85,6 +86,7 @@ static const struct amdxdna_dev_priv npu2_dev_priv = { >>           DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU2_PSP, MP0_C2PMSG_73), >>           DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123), >>           DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU2_REG, >> MPNPU_PUB_SCRATCH3), >> +        DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU2_REG, >> MPNPU_PWAITMODE), >>       }, >>       .smu_regs_off   = { >>           DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU2_SMU, MP1_C2PMSG_0), >> diff --git a/drivers/accel/amdxdna/npu4_regs.c >> b/drivers/accel/amdxdna/npu4_regs.c >> index 986a5f28ba24..4ca21db70478 100644 >> --- a/drivers/accel/amdxdna/npu4_regs.c >> +++ b/drivers/accel/amdxdna/npu4_regs.c >> @@ -13,6 +13,7 @@ >>   #include "amdxdna_pci_drv.h" >>     /* NPU Public Registers on MpNPUAxiXbar (refer to Diag >> npu_registers.h) */ >> +#define MPNPU_PWAITMODE                0x301003C >>   #define MPNPU_PUB_SEC_INTR             0x3010060 >>   #define MPNPU_PUB_PWRMGMT_INTR         0x3010064 >>   #define MPNPU_PUB_SCRATCH0             0x301006C >> @@ -116,6 +117,7 @@ static const struct amdxdna_dev_priv >> npu4_dev_priv = { >>           DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU4_PSP, MP0_C2PMSG_73), >>           DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123), >>           DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU4_REG, >> MPNPU_PUB_SCRATCH3), >> +        DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU4_REG, >> MPNPU_PWAITMODE), >>       }, >>       .smu_regs_off   = { >>           DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU4_SMU, MP1_C2PMSG_0), >> diff --git a/drivers/accel/amdxdna/npu5_regs.c >> b/drivers/accel/amdxdna/npu5_regs.c >> index 75ad97f0b937..f761a6661f40 100644 >> --- a/drivers/accel/amdxdna/npu5_regs.c >> +++ b/drivers/accel/amdxdna/npu5_regs.c >> @@ -13,6 +13,7 @@ >>   #include "amdxdna_pci_drv.h" >>     /* NPU Public Registers on MpNPUAxiXbar (refer to Diag >> npu_registers.h) */ >> +#define MPNPU_PWAITMODE                0x301003C >>   #define MPNPU_PUB_SEC_INTR             0x3010060 >>   #define MPNPU_PUB_PWRMGMT_INTR         0x3010064 >>   #define MPNPU_PUB_SCRATCH0             0x301006C >> @@ -62,7 +63,7 @@ >>   #define NPU5_SRAM_BAR_BASE    MMNPU_APERTURE1_BASE >>     static const struct amdxdna_dev_priv npu5_dev_priv = { >> -    .fw_path        = "amdnpu/17f0_11/npu.sbin", >> +    .fw_path        = "amdnpu/17f0_11/npu.dev.sbin", > > This seems like an unintended change. Ah. Yes. It is a merging issue. Sorry about the confusion. Thanks, Lizhi > >>       .protocol_major = 0x6, >>       .protocol_minor = 12, >>       .rt_config    = npu4_default_rt_cfg, >> @@ -85,6 +86,7 @@ static const struct amdxdna_dev_priv npu5_dev_priv = { >>           DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU5_PSP, MP0_C2PMSG_73), >>           DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123), >>           DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU5_REG, >> MPNPU_PUB_SCRATCH3), >> +        DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU5_REG, >> MPNPU_PWAITMODE), >>       }, >>       .smu_regs_off   = { >>           DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU5_SMU, MP1_C2PMSG_0), >> diff --git a/drivers/accel/amdxdna/npu6_regs.c >> b/drivers/accel/amdxdna/npu6_regs.c >> index 758dc013fe13..1f71285655b2 100644 >> --- a/drivers/accel/amdxdna/npu6_regs.c >> +++ b/drivers/accel/amdxdna/npu6_regs.c >> @@ -13,6 +13,7 @@ >>   #include "amdxdna_pci_drv.h" >>     /* NPU Public Registers on MpNPUAxiXbar (refer to Diag >> npu_registers.h) */ >> +#define MPNPU_PWAITMODE                0x301003C >>   #define MPNPU_PUB_SEC_INTR             0x3010060 >>   #define MPNPU_PUB_PWRMGMT_INTR         0x3010064 >>   #define MPNPU_PUB_SCRATCH0             0x301006C >> @@ -85,6 +86,7 @@ static const struct amdxdna_dev_priv npu6_dev_priv = { >>           DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU6_PSP, MP0_C2PMSG_73), >>           DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123), >>           DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU6_REG, >> MPNPU_PUB_SCRATCH3), >> +        DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU6_REG, >> MPNPU_PWAITMODE), >>       }, >>       .smu_regs_off   = { >>           DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU6_SMU, MP1_C2PMSG_0), >