From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18044C433EF for ; Tue, 9 Nov 2021 09:50:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01462611CC for ; Tue, 9 Nov 2021 09:49:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245053AbhKIJwo (ORCPT ); Tue, 9 Nov 2021 04:52:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244252AbhKIJvg (ORCPT ); Tue, 9 Nov 2021 04:51:36 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B69FC06120F for ; Tue, 9 Nov 2021 01:48:42 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id o14so19935085plg.5 for ; Tue, 09 Nov 2021 01:48:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SHTUtS2AqMwL7pythy2uWZaJGxfuuKizfBg8h7XFuhk=; b=GTvbZO/Gy+t/HbdqxXnGSSUAYcX19EgyiDh4hSzeDsksdaBW6HwN7DfqsqaO4pey2/ jTJ9RHZW4nslizMrt1R/QL8IZf5LPZtAeLV9sANL6ww2ozo8lj8EL4aZio924rPaP/IM 6B5RjEwqDaSqfZadOtwe0nCFHmMRsvQopFZ1T0JhRi3Wo6t5SeUUDkWiNTD2X0Mb6lUh xinKcpR9Yyxnk6b53anjGiZTbPyu1gigcVFn4dfoK+OWU+/pe1tDQG2gLHEJvDcHL+CA jOt+xmi9YhvrZd2t2q1D/jGaHtsZ6uHek+ITnPfOzOmEx8rSMKBJSo+6ZJwe2VlAqoz6 d0mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SHTUtS2AqMwL7pythy2uWZaJGxfuuKizfBg8h7XFuhk=; b=oSzNW/IYA6C7zePw99pGTX3NlEpDdTUjhaNY91VczJqSE4exHwLjYSEp3arhvaJZ2e efE1TdHfX1oprA2wcw8Th78fp/bpqMYTFsDXTZnqs2a4Bvz2Yg+EWH915eGSOtBgnw55 neoG5HFSkSU4t7nnVDc+3wSKE7Ww0AyRyFqqtWm4I7r0WUVEnri4Kyi5+WBUxgsRhTr0 9vH8a+8k68uVt/w7/lpB4JZyXhm5iPp0DCgb3ssVsWN8pRSg3IKiP8CKV21FzTF11Lnu ypT6esLbq3I6zdMtH9/HcplljgfC6klmW8FZ+hpdY8Ku8RYwzsNIjjzI/LJGIwxxMnfD Opuw== X-Gm-Message-State: AOAM532IfVQFyfCEfcngLnA2KQFud7iPB9327Dcryr5dEoyswbCxePmq HYhIqXuCwnHyu3iV3JSpiY86Dw== X-Google-Smtp-Source: ABdhPJz4uumb1qUyFkc+MgaWMH/uDR5/ELb0ybuZChURb8fO/VbIhSArnl8zYY0FjHOCybWkDdacyw== X-Received: by 2002:a17:90a:9907:: with SMTP id b7mr2476181pjp.137.1636451321564; Tue, 09 Nov 2021 01:48:41 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv1sm1940511pjb.48.2021.11.09.01.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Nov 2021 01:48:41 -0800 (PST) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features. Date: Tue, 9 Nov 2021 17:48:18 +0800 Message-Id: <8652c476f08626d52f0412ca1a8427cfe7b4104f.1636362169.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@linux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen --- arch/riscv/kernel/cpufeature.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7069e55335d0..8e7557980faf 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -21,6 +21,11 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; #ifdef CONFIG_FPU __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); #endif +#ifdef CONFIG_VECTOR +#include +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector); +unsigned long riscv_vsize __read_mostly; +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -149,4 +154,12 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) static_branch_enable(&cpu_hwcap_fpu); #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + static_branch_enable(&cpu_hwcap_vector); + /* There are 32 vector registers with vlenb length. */ + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } -- 2.31.1