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b=CScedXiwOE2QuyRVGyi63GwLH1qDWROo+KlulADZp632qg9ca4pgG9FBdu7tHIsncjzyt6Y+fJsckvxikTGhYA9nUE+fU0yH8Zhgu0fp4uxc5TezaxWlE6WVXE+xfcjDfxT4F5YsVeffci+aL41KpElISdBgyQN5+bB+d7tYGM8= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB10391.eurprd08.prod.outlook.com (2603:10a6:800:20c::6) by DBBPR08MB6235.eurprd08.prod.outlook.com (2603:10a6:10:201::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.71.14; Thu, 28 May 2026 12:07:22 +0000 Received: from VI0PR08MB10391.eurprd08.prod.outlook.com ([fe80::fa6b:9ba8:5c2f:ac91]) by VI0PR08MB10391.eurprd08.prod.outlook.com ([fe80::fa6b:9ba8:5c2f:ac91%3]) with mapi id 15.21.0071.010; Thu, 28 May 2026 12:07:21 +0000 Message-ID: <86780f97-29ee-4a72-b311-38c89434b707@arm.com> Date: Thu, 28 May 2026 14:07:19 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] ACPI: CPPC: Add ospm_nominal_perf support To: Sumit Gupta , rafael@kernel.org, viresh.kumar@linaro.org, lenb@kernel.org, zhenglifeng1@huawei.com, zhanjie9@hisilicon.com, mario.limonciello@amd.com, saket.dumbre@intel.com, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, acpica-devel@lists.linux.dev Cc: treding@nvidia.com, jonathanh@nvidia.com, vsethi@nvidia.com, ksitaraman@nvidia.com, sanjayc@nvidia.com, bbasu@nvidia.com References: <20260514194822.1841748-1-sumitg@nvidia.com> <20260514194822.1841748-3-sumitg@nvidia.com> <457972d4-eabd-4db9-8d82-b4c6a5f79465@arm.com> <5bf877d5-42b8-4e0d-9afd-6cb9c4b45bb1@nvidia.com> Content-Language: en-US From: Pierre Gondois In-Reply-To: <5bf877d5-42b8-4e0d-9afd-6cb9c4b45bb1@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Vr7kUfBxD2yxIdDU3J0U5UW1/+xBkZZg6Mbcf6E91JrHoHKxO9FW2rAa6ngSEgwEbLFplVoQv/seOXY/TBizfRdMHn+ePXpSqGT6YGuKwpTX+Ho8zIiZD4nd+4uZHz7YzH1krmVJmFmDwB3D7XH49eQXtVeXalyjJTGWqalAV6FG5P7wvGt6DF2BDHk9roqSeGHdUQP0FInBz0NY2YAtMIEW+drtRQ8bWoswPvnIH33wo0aS793mGawk2uIRnzjZb4JM88iD0AzxgECEKtlkS3qvjRIITB5CI1S66yio5s2N/Q90G1MnZMhmVQ/PZ6JB1SaJFsQhsQBH2Pg32qg5a9OdlLWwGdE3CtuGRrXLkepZXTpag2DLb58h2cAKKKmi9jGz7vE7gLkDrN0/XVMlwHfGKY2Yb+NF8WPL6MuhQmjLHjlXI46wXyCZ3M1dHdaM X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 12:08:25.2318 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73eeb0db-e578-4a01-077c-08debcb1d219 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C713.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB11455 Hello Sumit, > > Hi Pierre, > > Thanks for the review and the complementary patch. > Going point by point: > > 1. Rollback for a partially applied multiple CPU write in >     store_ospm_nominal_freq(): Agreed, will add into v4. > > 2. cppc_get_ospm_nominal_perf() and the show/init/exit coherence >     checks that rely on it: I'd skip these as the register is write-only >     as per spec. > NIT: IIUC having a write-only register doesn't mean we cannot read it. Cf. cppc_get_desired_perf() > 3. Initializing the register at startup and restoring at exit: In v3, we >     dropped the unconditional cpu_init write so user values would >     survive CPU hotplug. The spec also makes the explicit init >     unnecessary: "If this register is not provided, then OSPM must >     assume that the OSPM Nominal Performance value is equal to >     the Nominal Performance value.". The unwritten default already >     looks well defined. The concern I had was for the scenario where: - the driver is loaded - the user sets an ospm_nominal_freq value - the driver is unloaded In such case, the ospm_nominal_freq value will still be set to a non-default value. The modifications suggested previously would allow to handle that case to come back to the default value. FWIU, we have: +------+     +---------+     +-----------+     +------+ | User | <-> | CPPC    | <-> | CPPC      | <-> | CPPC | +------+     | driver  |     | reg       |     | HW   |              +---------+     | interface |     | reg  |                              +-----------+     +------+ So if we want to handle: - the case described above - the case you mentioned, i.e. hot-plugging CPUs maybe the scratch values should be stored along the CPPC register interface. This would allow to handle complex cases where CPUs are hotplugged and the driver is loaded/unloaded ? Note: the same kind of scenario should apply to the auto_sel register > 4. pr_warn() in show_ospm_nominal_freq() on HW vs cache >     mismatch: Skipping it since it relies on (2). > > So in v4, will pick up the rollback and leave the rest as is. > Happy to discuss further if you think differently.